Semiconductor device and method of forming a low profile dual-purpose shield and heat-dissipation structure

Patent metadata

Field	Value
Publication number	US-10163744-B2
Application number	US-201113226767-A
Country	US
Kind code	B2
Filing date	Sep 7, 2011
Priority date	Sep 7, 2011
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A semiconductor device has a substrate including a recess and a peripheral portion with through conductive vias. A first semiconductor die is mounted over the substrate and within the recess. A planar heat spreader is mounted over the substrate and over the first semiconductor die. The planar heat spreader has openings around a center portion of the planar heat spreader and aligned over the peripheral portion of the substrate. A second semiconductor die is mounted over the center portion of the planar heat spreader. A third semiconductor die is mounted over the second semiconductor die. First and second pluralities of bond wires extend from the second and third semiconductor die, respectively, through the openings in the planar heat spreader to electrically connect to the through conductive vias. An encapsulant is deposited over the substrate and around the planar heat spreader.

First claim

What is claimed:

1. A semiconductor device, comprising:
a substrate including a recess formed partially through the substrate;
a conductive via formed through a surface of the substrate;
a first semiconductor die disposed within the recess over the conductive via;
a planar shaped heat spreader in thermal contact with the first semiconductor die;
a second semiconductor die disposed over the planar shaped heat spreader; and
a first bond wire extending from the second semiconductor die through an opening in the planar shaped heat spreader to the substrate.

2. The semiconductor device of claim 1 , further including:
a third semiconductor die disposed over the second semiconductor die; and
a second bond wire extending from the third semiconductor die through the opening in the planar shaped heat spreader to the substrate.

3. The semiconductor device of claim 1 , wherein the planar shaped heat spreader includes a roughened surface.

4. The semiconductor device of claim 1 , further including a support structure extending orthogonally from the planar shaped heat spreader.

5. The semiconductor device of claim 1 , wherein the planar shape of the planar shaped heat spreader reduces a vertical profile of the semiconductor device and increases manufacturability.

6. A semiconductor device, comprising:
a first substrate including a recess formed partially through the first substrate;
a conductive via formed through a surface of the first substrate;
a first semiconductor die disposed within the recess;
a heat spreader including a planar surface in thermal contact with the first semiconductor die;
a second semiconductor die disposed over the heat spreader; and
a first bond wire extending through an opening in the heat spreader to the substrate.

7. The semiconductor device of claim 6 , further including a third semiconductor die disposed over the second semiconductor die.

8. The semiconductor device of claim 6 , wherein the heat spreader includes copper, aluminum, stainless steel, nickel silver, low-carbon steel, or other metal and composite comprising high thermal conductivity capable of blocking or absorbing electromagnetic interference, radio frequency interference, harmonic distortion, or other inter-device interference.

9. The semiconductor device of claim 6 , wherein the planar surface of the heat spreader reduces a vertical profile of the semiconductor device and increases manufacturability.

10. A semiconductor device, comprising:
a substrate including a recess;
a conductive via formed through a surface of the substrate;
a first semiconductor die disposed within the recess, wherein an active surface of the first semiconductor die is oriented toward the substrate and electrically connected to the conductive via;
a shield disposed over a non-active surface of the first semiconductor die opposite the active surface and electrically connected to the substrate;
a second semiconductor die disposed over the shield;
a third semiconductor die disposed over the second semiconductor die; and
a bond wire extending from the third semiconductor die through an opening in the shield to the substrate.

11. A semiconductor device, comprising:
a substrate including a recess;
a conductive via formed through a surface of the substrate;
a first semiconductor die disposed within the recess, wherein an active surface of the first semiconductor die is oriented toward the substrate and electrically connected to the conductive via;
a shield disposed over a non-active surface of the first semiconductor die opposite the active surface and electrically connected to the substrate;
a second semiconductor die disposed over the shield; and
a bond wire extending from the second semiconductor die through an opening in the shield to the substrate.

12. The semiconductor device of claim 11 , wherein the shield includes copper, aluminum, stainless steel, nickel silver, low-carbon steel, or other metal and composite comprising high thermal conductivity capable of blocking or absorbing electromagnetic interference, radio frequency interference, harmonic distortion, or other inter-device interference.

13. The semiconductor device of claim 11 , wherein the shield extends to a perimeter of the substrate.

14. The semiconductor device of claim 1 , wherein the planar shaped heat spreader includes copper, aluminum, stainless steel, nickel silver, low-carbon steel, or other metal and composite comprising high thermal conductivity capable of blocking or absorbing electromagnetic interference, radio frequency interference, harmonic distortion, or other inter-device interference.

Assignees

• Kim Ohhan
• Ko Wonjun
• Choi Daesik
• Stats Chippac Pte Ltd

Inventors

• Kim Ohhan
• Ko Wonjun
• Choi Daesik

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title