Semiconductor device and a method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10163718-B2
Application number	US-201715699643-A
Country	US
Kind code	B2
Filing date	Sep 8, 2017
Priority date	Dec 31, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a first structure disposed in a first opening, the first structure including a first gate dielectric layer, a first first-conductive layer on the first gate dielectric layer, a first second-conductive layer on the first first-conductive layer and a first third-conductive layer disposed on the first second-conductive layer, and a second structure disposed in a second opening, the second structure including a second gate dielectric layer, a second first-conductive layer on the second gate dielectric layer and a second third-conductive layer on the second first-conductive layer;
recessing the first structure and the second structure; and
forming a first fourth-conductive layer over the recessed first structure, and a second fourth-conductive layer over the recessed second structure,
wherein in the recessing, the first and second gate dielectric layers are also recessed.

2. The method of claim 1 , wherein:
the first opening is formed by first sidewall spacers and the second opening is formed by second sidewall spacers, and
an insulating layer is disposed over the first sidewall spacers and the second sidewall spacers.

3. The method of claim 2 , further comprising, after the first and second structures are formed and before the recessing the first and second structures, recessing the first and second sidewall spacers and the insulating layer.

4. The method of claim 1 , further comprising forming a first fifth-conductive layer over the first third-conductive layer before forming the first fourth-conductive layer and a second fifth-conductive layer over the second third-conductive layer before forming the second fourth-conductive layer.

5. The method of claim 1 , wherein a material of the first and second third-conductive layers is the same and include at least one of W, Co, Ti, Al, and Cu.

6. The method of claim 1 , wherein a material of the first second-conductive layer and the first first-conductive layer is the same and include at least one of TiN, Al, TaAlC and TiAl.

7. The method of claim 1 , wherein a material of the first first-conductive layer includes at least one of TiN, TaN and Ti.

8. A method of manufacturing a semiconductor device, the method comprising:
forming a first structure for a first field effect transistor (FET) having a gate length Lg1 and forming a second structure for a second field effect transistor (FET) having a gate length Lg2 larger than Lg1, the first structure being disposed in a first opening, the first structure including a first gate dielectric layer, a first first-conductive layer on the first gate dielectric layer, a first second-conductive layer on the first first-conductive layer and a first third-conductive layer disposed on the first second-conductive layer, and the second structure being disposed in a second opening, the second structure including a second gate dielectric layer, a second first-conductive layer on the second gate dielectric layer and a second third-conductive layer on the second first-conductive layer;
covering the second structure with a mask layer;
recessing the first structure, while the second structure is covered with the mask layer;
forming a first fourth-conductive layer over the first first-conductive layer, the first second-conductive layer and the first third-conductive layer, while the second structure is covered with the mask layer;
after forming the first fourth-conductive layer, removing the mask layer; and
recessing the first fourth-conductive layer and the second structure.

9. The method of claim 8 , wherein after recessing the first structure, the first third-conductive layer protrudes from the first first-conductive layer and the first second-conductive layer.

10. The method of claim 8 , wherein after recessing the second structure, the second third-conductive layer protrudes from the second first-conductive layer.

11. The method of claim 8 , wherein after recessing the first fourth-conductive layer and the second structure, a height of the recessed first fourth-conductive layer from a substrate is different from a height of the recessed second third-conductive layer from the substrate.

12. The method of claim 8 , further comprising forming a fifth conductive layer over the first third-conductive layer before forming the first fourth-conductive layer.

13. The method of claim 8 , further comprising, after recessing the first fourth-conductive layer and the second structure,
forming a first cap insulating layer over the recessed first fourth-conductive layer and a second cap insulating layer over the recessed second third-conductive layer and the second first-conductive layer.

14. The method of claim 8 , wherein a material of the first third-conductive layer is the same as a material of the first fourth-conductive layer.

15. The method of claim 8 , wherein a material of the first and second third-conductive layers includes at least one of W, Co, Ti, Al, and Cu.

16. The method of claim 8 , wherein a material of the first second-conductive layer includes at least one of TiN, Al, TaAlC and TiAl.

17. The method of claim 8 , wherein a material of the first first-conductive layer includes at least one of TiN, TaN and Ti.

18. A semiconductor device comprising:
a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode, the first FET having a gate length Lg1; and
a second FET including a second gate dielectric layer and a second gate electrode, the second FET having a gate length Lg2 greater than Lg1, wherein:
the first gate electrode includes a first lower conductive layer, a first upper conductive layer and an intermediate conductive layer disposed between the first lower conductive layer and the first upper conductive layer,
the first lower conductive layer includes a first underlying conductive layer in contact with the first gate dielectric layer, a second underlying conductive layer on the first underlying conductive layer and a first bulk conductive layer,
the first bulk conductive layer protrudes from the first and second underlying conductive layers,
the second gate electrode includes a third underlying conductive layer and a second bulk conductive layer,
a bottom of the third underlying conductive layer is in contact with the second gate dielectric layer, and
an insulating layer is provided in contact with an upper surface of the third underlying conductive layer and an upper surface of the second gate dielectric layer.

19. The semiconductor device of claim 18 , wherein a height of the first upper conductive layer from a substrate is different from a height of the second bulk conductive layer from the substrate.

20. The semiconductor device of claim 18 , wherein:
the first underlying conductive layer includes at least one of TiN, TaN and Ti, and the second and third underlying conductive layer is made of a different material than the first underlying conductive layer and includes at least one of TiN, Al, TaAlC and TiAl.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Li Po-Hsueh
• Yeh Chih-Yang
• Hsiao Chun-Chan
• Yeh Kuan-Lin
• Huang Yuan-Sheng

Classifications

• H01L29/66545

  Electricity · mapped topic

• H01L29/4966

  Electricity · mapped topic

• H01L29/42376

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic