Method and apparatus for stacking devices in an integrated circuit assembly

Patent metadata

Field	Value
Publication number	US-10163675-B2
Application number	US-201715629460-A
Country	US
Kind code	B2
Filing date	Jun 21, 2017
Priority date	Jun 24, 2016
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

Methods and apparatuses for stacking devices in an integrated circuit assembly are provided. A tray for supporting multiple dies of a semiconductor material enables both topside processing and bottom side processing of the dies. The dies can be picked and placed for bonding on a substrate or on die stacks without flipping the dies, thereby avoiding particulate debris from the diced edges of the dies from interfering and contaminating the bonding process. In an implementation, a liftoff apparatus directs a pneumatic flow of gas to lift the dies from the tray for bonding to a substrate, and to previously bonded dies, without flipping the dies. An example system allows processing of both top and bottom surfaces of the dies in a single cycle in preparation for bonding, and then pneumatically lifts the dies up to a target substrate so that topsides of the dies bond to bottom sides of dies of the previous batch, in an efficient and flip-free assembly of die stacks.

First claim

The invention claimed is:

1. An apparatus, comprising:
a die tray for supporting a semiconductor material for both topside processing and bottom side processing;
a bezel disposed on an interior perimeter of the die tray for supporting the semiconductor material at an edge of the semiconductor material; and
a through-hole in the die tray for enabling access to at least a bottom side of the semiconductor material for at least the bottom side processing; and
a liftoff member for directing a pneumatic flow of a gas to the bottom side of the semiconductor material for lifting the semiconductor material from the die tray to a substrate, a wafer, or a die.

2. The apparatus of claim 1 , wherein the through-hole enables access to an entire bottom side of the semiconductor material for the bottom side processing except for one or more areas of contact between the bezel and the edge of the semiconductor material.

3. The apparatus of claim 1 , further comprising bumps, spheres, hemispheres, ridges, nanowires, or pins on the bezel to reduce the one or more areas of contact between the bezel and the edge of the semiconductor material to increase the access to the bottom side of the semiconductor material.

4. The apparatus of claim 1 , wherein the die tray enables simultaneous topside processing and bottom side processing of the semiconductor material.

5. The apparatus of claim 1 , further comprising a hydrophobic layer or coating on the die tray.

6. The apparatus of claim 5 , wherein the hydrophobic layer comprises a scratch resistant surface.

7. The apparatus of claim 1 , wherein the through-hole enables access to the bottom side for a process selected from the group consisting of a cleaning operation, a coating removal process, a layer removal process, an activation process, a termination process, a laminating process, a bonding process, and a direct bond interconnect process.

8. The apparatus of claim 1 , wherein the die tray enables the semiconductor material to be picked up from the die tray and enables the bottom side of the semiconductor material to be attached to a substrate without flipping the semiconductor material.

9. A system, comprising:
a frame for holding a die of a semiconductor material while exposing a top and a bottom of the die for processing;
an interior rim of the frame for supporting the die at an edge of the die;
a tray composed of an array of the frames for processing multiple dies;
a liftoff apparatus attachable or mateable to a base of the tray; and
wherein the liftoff apparatus provides a pneumatic gas flow to push the multiple dies from the tray into contact with a wafer or a substrate, or onto respective dies of multiple die stacks, for bonding.

10. The system of claim 9 , wherein the interior rim comprises surface features to reduce a contact area between the interior rim and the edge of the die in order to increase an area of the bottom of the die available for the processing.

11. The system of claim 9 , wherein the tray composed of the array of the frames enables simultaneous removal of upper and lower die protective coatings, activation of top surfaces of the multiple dies, termination processing of the top surfaces of the multiple dies, and bonding of the multiple dies to a wafer, a substrate, or to respective multiple die stacks, without flipping the multiple dies.

12. The system of claim 11 , wherein the tray and the liftoff apparatus position the multiple dies to bond top surfaces of the multiple dies with the wafer, the substrate, or the respective multiple die stacks, while the bottom surfaces of the multiple dies are ready for bonding to a next placement of top surfaces of a next batch of multiple dies to be processed by the system, in an ongoing assembly of the multiple die stacks.

13. A system, comprising:
a frame for holding a die of a semiconductor material while exposing a top and a bottom of the die for processing;
an interior rim of the frame for supporting the die at an edge of the die;
a tray composed of an array of the frames for processing multiple dies; and
wherein the tray composed of the array of the frames enables simultaneous removal of upper and lower die protective coatings, activation of top surfaces of the multiple dies, termination processing of the top surfaces of the multiple dies, and bonding of the multiple dies to a wafer, a substrate, or to respective multiple die stacks, without flipping the multiple dies.

Assignees

• Invensas Corp

Inventors

• Uzoh Cyprian Emeka

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/07118

  Means for cleaning, e.g. brushes · CPC title

• H10W90/00

  Package configurations · CPC title