Method of forming semiconductor device using titanium-containing layer and device formed

Patent metadata

Field	Value
Publication number	US-10163643-B2
Application number	US-201715723541-A
Country	US
Kind code	B2
Filing date	Oct 3, 2017
Priority date	Dec 14, 2016
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A method of forming a semiconductor device includes etching an inter-layer dielectric (ILD) to form a contact opening exposing a portion of a source/drain (S/D). The method further includes depositing a titanium-containing material into the contact opening, wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of the ILD to form protrusions extending from a top surface of the S/D. The method further includes annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
etching an inter-layer dielectric (ILD) to form a contact opening exposing a portion of a source/drain (S/D);
depositing a titanium-containing material into the contact opening, wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of the ILD to form protrusions extending from a top surface of the S/D; and
annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions.

2. The method of claim 1 , further comprising filling the contact opening with a contact plug.

3. The method of claim 1 , wherein annealing the semiconductor device comprises forming the silicide layer comprising TiSi 2 or TiSiGe.

4. The method of claim 1 , wherein annealing the semiconductor device comprises forming a plurality of sub-regions in the S/D, wherein each sub-region of the plurality of sub-regions has a different percentage of components of the material of the S/D.

5. The method of claim 4 , wherein annealing the semiconductor device comprises forming a first sub-region of the S/D closest to the silicide layer having a lowest concentration of Ge among the plurality of sub-regions.

6. The method of claim 1 , wherein depositing the titanium-containing material comprises depositing titanium or titanium nitride.

7. The method of claim 1 , wherein depositing the titanium-containing material comprises depositing the titanium-containing material with sufficient energy to form the protrusions having a height above the top surface of the S/D ranging from about 3 nanometers (nm) to about 7 nm.

8. The method of claim 1 , wherein depositing the titanium-containing material comprises depositing the titanium-containing material with sufficient energy to form the protrusions having a width adjacent to the top surface of the S/D ranging from about 4 nm to about 6 nm.

9. The method of claim 1 , wherein depositing the titanium-containing material comprises depositing the titanium-containing material with sufficient energy to form the protrusions having a tapered profile.

10. A method of forming a semiconductor device, the method comprising:
etching an inter-layer dielectric (ILD) to form a contact opening exposing a portion of a source/drain (S/D), wherein the S/D comprises silicon germanium (SiGe);
depositing a titanium-containing material into the contact opening, wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of the SiGe along sidewalls of the ILD to form protrusions; and
annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions, wherein, following the annealing, the S/D comprises a first region having a first germanium concentration and a second region having a second germanium concentration different from the first germanium concentration.

11. The method of claim 10 , wherein annealing the semiconductor device comprises forming the first region adjacent to the silicide layer having a lower germanium concentration than the second region.

12. The method of claim 11 , wherein annealing the semiconductor device comprises forming a third region in the S/D between the first region and the second region.

13. The method of claim 12 , wherein annealing the semiconductor device comprises forming the third region having a higher germanium concentration than the second region.

14. The method of claim 10 , wherein annealing the semiconductor device comprise forming the protrusions having a tapered profile.

15. The method of claim 10 , wherein etching the ILD comprises forming the contact opening extending over a gate structure of the semiconductor device.

16. A semiconductor device comprising:
a gate structure on a substrate;
a source/drain (S/D) in the substrate and adjacent to the gate structure, wherein the S/D comprises protrusions extending from a top surface of the S/D, and the protrusions have a tapered profile;
a silicide layer in the protrusions and along the top surface of the S/D, wherein the silicide layer comprises titanium; and
a contact plug electrically connected to the S/D through the silicide layer.

17. The semiconductor device of claim 16 , wherein the S/D comprises a first region having a first germanium concentration and a second region having a second germanium concentration different from the first germanium concentration.

18. The semiconductor device of claim 17 , wherein the first region is adjacent to the silicide layer.

19. The semiconductor device of claim 17 , wherein the S/D further comprises a third region between the first region and the second region, and the third region has a higher germanium concentration than the second region.

20. The semiconductor device of claim 16 , wherein the silicide layer extends between adjacent protrusions.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Chia-Yang
• Jangjian Shiu-Ko
• Chang Keng-Chuan
• Su Ting-Siang

Classifications

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10P14/42

  using a gas or vapour · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title