Semiconductor device and operating method thereof

Patent metadata

Field	Value
Publication number	US-10163523-B2
Application number	US-201815866094-A
Country	US
Kind code	B2
Filing date	Jan 9, 2018
Priority date	Mar 31, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.

First claim

What is claimed is:

1. A method of operating a semiconductor memory device including a plurality of pages coupled to a plurality of word lines, the method comprising:
performing a program operation on each of the plurality of pages by using an incremental step pulse program (ISPP) method using a determined verify voltage;
providing an additional program pulse at least once to the plurality of pages through the plurality of word lines; and
detecting a defective page from the plurality of pages by performing read operations on the plurality of pages through a reference test voltage greater than the determined verify voltage.

2. The method of claim 1 ,
wherein the plurality of pages are stacked over a substrate, and
wherein each of the plurality of pages is coupled to a corresponding word line located at a predetermined height from the substrate.

3. The method of claim 1 , wherein the detecting of the defective page comprises:
detecting first and second page data by performing read operations on first and second pages, respectively, among the plurality of pages;
generating a first comparative page by performing an OR operation on data bits of the first and second page data; and
generating a first error value according to a number of fail bits of the first comparative page.

4. The method of claim 3 , wherein the detecting of the defective page further comprises:
detecting third page data by performing a read operation on a third page among the plurality of pages;
generating a second comparative page by performing an OR operation on the data bits of the second and third page data;
generating a second error value according to a number of fail bits of the second comparative page; and
detecting the third page as the defective page by comparing the second error value with the first error value.

5. The method of claim 1 , wherein the detecting of the defective page comprises:
detecting first page data by performing a read operation on a first page among the plurality of pages;
generating a first error value according to a number of fail bits in the first page data;
detecting second page data by performing a read operation on a second page among the plurality of pages;
generating a second error value according to a number of fail bits in the second page data; and
detecting the second page as the defective page by comparing the second error value with the first error value.

6. The method of claim 1 , wherein the detecting of the defective page comprises:
detecting page data by performing a read operation on one of the plurality of pages; and
detecting a corresponding page as the defective page when a number of fail bits in the page data is greater than a reference value.

7. The method of claim 1 , wherein a region corresponding to the defective page is defined as a bad region.

8. A semiconductor memory device, comprising:
a memory cell array including a plurality of memory blocks, each of which includes a plurality of pages coupled to each of the plurality of word lines; and
a peripheral circuit suitable for performing a program operation on each of the plurality of pages,
wherein during the program operation, the peripheral circuit performs the program operation on a selected page, verifies whether or not a result of the program operation is a pass by applying a verify voltage to a word line of the selected page, and
repeats programming and verifying until the result of the program operation is the pass, and
wherein the peripheral circuit further increases threshold voltages of memory cells included in the plurality of pages by applying an additional program pulse at least once to the plurality of word lines, and detects a defective page among the plurality of pages by performing read operations on the plurality of pages through a reference test voltage greater than the verify voltage by an amount of a determined voltage.

9. The semiconductor memory device of claim 8 ,
wherein the plurality of pages are stacked over a substrate, and
wherein each of the plurality of pages is coupled to a corresponding word line located at a predetermined height from the substrate.

10. The semiconductor memory device of claim 8 , wherein the peripheral circuit detects the defective page by:
detecting first and second page data by performing read operations on first and second pages, respectively, among the plurality of pages,
generating a first comparative page by performing an OR operation on data bits of the first and second page data,
detecting third page data by performing a read operation on a third page among the plurality of pages, and
generating a second comparative page by performing an OR operation on data bits of the second and third page data.

11. The semiconductor memory device of claim 10 , wherein the peripheral circuit comprises:
a detector suitable for generating a first error value according to a number of fail bits of the first comparative page and a second error value according to a number of fail bits of the second comparative page; and
a control logic suitable for detecting the third page as the defective page by comparing the second error value with the first error value.

12. The semiconductor memory device of claim 8 , wherein a region corresponding to the defective page is defined as a bad region.

Assignees

• Sk Hynix Inc

Inventors

• Won Sam Kyu
• Kim Myung Su
• Cha Jae Won

Classifications

• G11C29/025 Primary

  in signal lines · CPC title

• G11C29/12005

  comprising voltage or current generators · CPC title

• G11C29/50004

  of threshold voltage · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C2029/1202

  Word line control · CPC title