Selective performance level modes of operation in a non-volatile memory

Patent metadata

Field	Value
Publication number	US-10163502-B2
Application number	US-201615396251-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Dec 30, 2016
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described.

First claim

What is claimed is:

1. An apparatus for use with a processor and a non-volatile memory having a bitcell, the apparatus comprising:
a multi-read mode memory controller configured to control the non-volatile memory in a selectable read mode in response to commands from the processor, said memory controller including:
multi-read mode selection logic configured to select a memory mode from a plurality of memory modes including a first memory mode, and a second memory mode;
multi-pulse width selection logic configured to select a read pulse width from a plurality of widths in association with the selected memory mode, said plurality of widths including a first read pulse width having a first read latency in the first memory mode, and a second read pulse width having a second read latency in the second read mode, wherein the second read pulse width is shorter than the first read pulse width, and the second read latency is shorter than the first read latency;
read logic configured to apply in a read operation in a selected memory mode, a read pulse having a selected read pulse width, to a bitcell of the non-volatile memory, to read a memory state stored in the bitcell wherein a memory state in the second read mode has a shorter persistence level than a memory state in the first read mode;
multi-refresh rate selection logic configured to select a refresh rate from a plurality of refresh rates as a function of one of the selected memory mode and the selected read pulse width, wherein the plurality of refresh rates include a first refresh rate at a first frequency in the first memory mode, and a second refresh rate at a second frequency in the second memory mode wherein the frequency of the second refresh rate is more frequent than the frequency of the first refresh rate; and
refresh logic configured to apply in a selected memory mode, memory refresh operations to the non-volatile memory at a selected refresh rate of the selected memory mode.

2. The apparatus of claim 1 wherein the second frequency of refresh operations is within a range of 10-100 times more frequent than the first frequency of refresh operations.

3. The apparatus of claim 1 , wherein the memory controller further comprises:
command logic configured to receive a command from the processor, wherein the multi-read mode selection logic is further configured to select a memory mode in response to a command received by the command logic.

4. The apparatus of claim 3 , wherein the multi-pulse width selection logic is further configured to select a read pulse width in response to a command received by the command logic.

5. The apparatus of claim 4 , wherein the command logic is further configured to receive a variable read pulse width value, and wherein the multi-pulse width selection logic is further configured to program the width of a read pulse as a function of the received variable read pulse width value to provide a programmable read pulse width so that the first and second memory modes are programmable memory modes in which read latency in each programmable memory mode is programmable, as a function of a programmable read pulse width.

6. The apparatus of claim 3 , wherein the command logic is further configured to receive a variable refresh rate value, and wherein the multi-refresh rate selection logic is further configured to program a refresh rate as a function of the received variable refresh rate value so that the first and second memory modes are programmable memory modes in which persistence level in each programmable memory mode is programmable, as a function of a programmable read pulse width.

7. The apparatus of claim 6 wherein the non-volatile memory is a phase change memory having a variable persistence level as a function of a variable read pulse width.

8. A method, comprising:
controlling a non-volatile memory in a selectable read mode in response to commands from a processor, said controlling including:
selecting a memory mode from a plurality of memory modes including a first memory mode, and a second memory mode;
selecting a read pulse width from a plurality of widths in association with the selected memory mode, said plurality of widths including a first read pulse width having a first read latency in the first memory mode, and a second read pulse width having a second read latency in the second read mode, wherein the second read pulse width is shorter than the first read pulse width, and the second read latency is shorter than the first read latency;
applying in a read operation in a selected memory mode, a read pulse having a selected read pulse width, to a bitcell of the non-volatile memory, to read a memory state stored in the bitcell wherein a memory state in the second read mode has a shorter persistence level than a memory state in the first read mode;
selecting a refresh rate from a plurality of refresh rates as a function of one of the selected memory mode and the selected read pulse width, wherein the plurality of refresh rates include a first refresh rate at a first frequency in the first memory mode, and a second refresh rate at a second frequency in the second memory mode wherein the frequency of the second refresh rate is more frequent than the frequency of the first refresh rate; and
applying in a selected memory mode, memory refresh operations to the non-volatile memory at a selected refresh rate of the selected memory mode.

9. The method of claim 8 wherein the second frequency of refresh operations is within a range of 10-100 times more frequent than the first frequency of refresh operations.

10. The method of claim 8 , wherein selecting a memory mode comprises:
receiving a memory mode command from the processor, and selecting a memory mode in response to a received memory mode command.

11. The method of claim 10 , wherein selecting a read pulse width includes receiving a read pulse width command from the processor and selecting a read pulse width in response to a received read pulse width command.

12. The method of claim 11 , wherein the received read pulse width command includes a variable read pulse width value, and wherein the selecting a read pulse width in response to a received variable read pulse width command includes programming the width of a read pulse as a function of the received read pulse width value to provide a programmable read pulse width so that the first and second memory modes are programmable memory modes in which read latency in each programmable memory mode is programmable, as a function of a programmable read pulse width.

13. The method of claim 8 , wherein the selecting a refresh rate includes receiving a refresh rate command from the processor, which includes a variable refresh rate value, and in response to the received refresh rate command, programming a refresh rate as a function of the received variable refresh rate value so that the first and second memory modes are programmable memory modes in which persistence level in each programmable memory mode is programmable, as a function of a programmable read pulse width.

14. The method of claim 13 wherein the non-volatile memory is a phase change memory having a variable persistence level as a function of a variable read pulse width.

15. A system comprising:
a processor;
a non-volatile memory having a bitcell; and
a multi-read mode memory controller configured to control the non-volatile memory in a selectable read mode in response to commands from the processor, said memory controller including:
multi-read mode selection logic configured to select a memory mode from a plurality of memory modes including a first memory mode, and a second

Assignees

• Intel Corp

Inventors

• Connor Christopher F
• Querbach Bruce
• Belgal Hanmant P

Classifications

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G06F3/0611

  in relation to response time · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title