Magnetic memory devices having memory cells and reference cells with different configurations

Patent metadata

Field	Value
Publication number	US-10163478-B2
Application number	US-201715603907-A
Country	US
Kind code	B2
Filing date	May 24, 2017
Priority date	Sep 6, 2016
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A semiconductor memory device includes a memory cell including a memory magnetic tunnel junction (MTJ) configured to be coupled to a first sensing node and a reference cell including a first resistance element and a second resistance element configured to be coupled in parallel to a second sensing node, the first resistance element including a first number of reference MTJs and the second resistance element including a second number of reference MTJs different from the first number of reference MTJs. The memory device further includes a sensing circuit configured to be coupled to the first and second sensing nodes and to detect a difference in resistance between the memory cell and the reference cell. In some embodiments, the first number of reference MTJs includes first reference MTJs connected in series and the second number of reference MTJs includes second reference MTJs connected in series.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell configured to be coupled to a first sensing node and including a memory MTJ programmable to first and second resistance states;
a reference cell configured to be coupled to a second sensing node and comprising a first reference MTJ having the second resistance state and second and third reference MTJs connected in series between first and second terminals of the first reference MTJ and each having the second resistance state; and
a sensing circuit configured to be coupled to the first and second sensing nodes and to detect a difference in resistance between the memory cell and the reference cell.

2. The semiconductor memory device of claim 1 , wherein each of the memory MTJ and the first, second and third reference MTJs comprises:
a first magnetic layer;
a second magnetic layer; and
a tunnel barrier layer between the first and second magnetic layers.

3. The semiconductor memory device of claim 2 , wherein each of the first, second and third reference MTJs has substantially the same structure and size as the memory MTJ.

4. The semiconductor memory device of claim 1 , wherein each of the memory MTJ and the first, second and third reference MTJs has an upper width less than its lower width, and wherein the upper width of each of the first, second and third reference MTJs is substantially the same as the upper width of the memory MTJ.

5. The semiconductor memory device of claim 1 , wherein each of the first, second and third reference MTJs comprises:
a pinned layer having a fixed magnetization direction;
a free layer having a changeable magnetization direction; and
a tunnel barrier layer between the pinned layer and the free layer,
wherein the magnetization directions of the pinned layer and the free layer are in an anti-parallel state.

6. The semiconductor memory device of claim 1 , further comprising a memory cell select element connected to the memory MTJ and a reference cell select element connected to the reference cell and wherein the cell select element and the reference cell select element are controlled by a common word line.

7. The semiconductor memory device of claim 1 , wherein the memory MTJ and the first, second and third reference MTJs are spin transfer torque (STT) MTJs.

Assignees

• Jung Hyunsung
• Jeong Daeeun
• Samsung Electronics Co Ltd

Inventors

• Jung Hyunsung
• Jeong Daeeun

Classifications

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title

• H01L43/02

  Electricity · mapped topic

• H01L43/10

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic