Cell layout of semiconductor device

Patent metadata

Field	Value
Publication number	US-10162925-B2
Application number	US-201514859162-A
Country	US
Kind code	B2
Filing date	Sep 18, 2015
Priority date	Sep 18, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A cell layout, a cell layout library and a synthesizing method are disclosed. The cell layout includes a cell block and a tapping connector. The cell block has a pin. The pin being disposed at a Nth metal layer in the cell layout. The tapping connector is disposed at a (N+1)th metal layer and a (N+2)th metal layer and stacked above the pin of the cell block. The tapping connector is electrically connected to the pin and forms an equivalent tapping point of the pin of the cell block. N is a positive integer greater than or equal to 1.

First claim

What is claimed is:

1. A device, comprising:
a cell block comprising a pin, the pin being disposed at a Nth metal layer in a cell layout; and
a tapping connector disposed at at least one metal layer above the Nth metal layer and stacked above the pin of the cell block, the tapping connector being electrically coupled to the pin and forming an equivalent tapping point of the pin of the cell block, wherein N is an integer greater than or equal to o,
wherein the equivalent tapping point and the pin are vertically overlapped, and fabrication of the device is initiated after a design rule check (DRC) or a signal electromagnetic (SEM) simulation test is passed,
wherein the tapping connector comprises:
a plurality of first metal interconnects disposed at a (N+1)th metal layer above the Nth metal layer, the plurality of first metal interconnects being parallel to each other, at least one of the plurality of first metal interconnects being stacked over the pin and being electrically coupled to the pin; and
at least one second metal interconnect disposed at a (N+2)th metal layer and stacked over the plurality of first metal interconnects, the second metal interconnect being electrically coupled to the plurality of first metal interconnects, and the at least one second metal interconnect forming the equivalent tapping point of the pin of the cell block.

2. The device of claim 1 , wherein a first width of one of the plurality of first metal interconnects is 1 to 3 times as wide as a minimum trace width on the (N+1)th metal layer according to design rules, a second width of the second metal interconnect is 1 to 3 times as wide as a minimum trace width on the (N+2)th metal layer according to the design rules, and the second width is 0.5 to 3 times as wide as the first width.

3. The device of claim 1 , wherein
the at least one second metal interconnect comprises: a plurality of second metal interconnects being stacked over and perpendicular to the plurality of first metal interconnects, the second metal interconnects being electrically coupled to the plurality of first metal interconnects, and the plurality of second metal interconnects forming the equivalent tapping point of the pin of the cell block.

4. The device of claim 3 , wherein a width of one of the plurality of first metal interconnects is 1 to 3 times as wide as a minimum trace width on the (N+1)th metal layer according to design rules.

5. The device of claim 1 , wherein a width of the at least one second metal interconnect is 1 to 3 times as wide as a minimum trace width on the (N+2)th metal layer according to design rules.

6. The device of claim 1 , wherein the cell block is stored in a cell layout library and regarded as a standard cell layout, the cell block and the tapping connector are stored in the cell layout library and regarded as a substitute cell layout of the standard cell layout.

7. The device of claim 6 , wherein the pin is a clock-related pin of the cell block and in response to the standard cell layout adopted in a synthesis process failing in the design rule check (DRC) or the signal electromagnetic (SEM) simulation test, the substitute cell layout is utilized to replace the standard cell layout in the synthesis process.

8. The device of claim 1 , further comprising:
a via array disposed between and connecting the at least one second metal interconnect and one of the plurality of first metal interconnects.

9. A device, comprising:
at least one substitute cell layout corresponding to a standard cell layout, the standard cell layout comprising a first cell block having a pin, each of the at least one substitute cell layout comprising a second cell block and a tapping connector, the second cell block being equivalent to the first cell block of the standard cell layout, the tapping connector being stacked above a pin of the second cell block, the tapping connector forming an equivalent tapping point of the pin of the second cell block,
wherein the tapping connector comprises:
a plurality of first metal interconnects disposed at a (N+1)th metal layer, the plurality of first metal interconnects being parallel to each other, at least one of the plurality of first metal interconnects being stacked over the pin of the second cell block and being electrically coupled to the pin of the second cell block; and
a second metal interconnect disposed at a (N+2)th metal layer and stacked over the plurality of first metal interconnects, the second metal interconnect being electrically coupled to the plurality of first metal interconnects, and the second metal interconnect forming the equivalent tapping point of the pin of the second cell block, and

wherein the equivalent tapping point and the pin of the second cell block are vertically overlapped, and fabrication of the device is initiated after a design rule check (DRC) or a signal electromagnetic (SEM) simulation test is passed.

10. The device of claim 9 , wherein the pin of the first cell block and the pin of the second cell block are clock-related pins, and the substitute cell layout is utilized to replace the standard cell layout failed in the design rule check (DRC) or the signal electromagnetic (SEM) simulation test.

11. The device of claim 9 , wherein the tapping connector within one substitute cell layout comprises widened metal interconnects pre-stacked above the pin of the second cell block.

12. The device of claim 11 , wherein a width of each widened metal interconnect is 1 to 3 times as wide as a minimum trace width on a corresponding metal layer according to design rules.

13. The device of claim 9 , wherein the tapping connector within one substitute cell layout comprises an interconnect-mesh pre-stacked above the pin of the second cell block.

14. The device of claim 13 , wherein the interconnect-mesh comprises a plurality of metal interconnects disposed on two different metal layers, the metal interconnects are electrically coupled to each other.

15. The device of claim 9 , wherein the second metal interconnect is perpendicular to the plurality of first metal interconnects.

16. The device of claim 9 , further comprising:
a via array disposed between and connecting the second metal interconnect and one of the plurality of first metal interconnects.

17. A method, comprising:
arranging standard cell layouts each comprising a first cell block having a pin and a tapping connector electrically coupled to the pin of the first cell block to form an equivalent tapping point of the pin of the first cell block, wherein the equivalent tapping point and the pin are vertically overlapped, and the tapping connector comprises a plurality of first metal interconnects and a second metal interconnect, the plurality of first metal interconnects being disposed at a (N+1)th metal layer and being parallel to each other, at least one of the plurality of first metal interconnects being stacked over the pin and being electrically coupled to the pin, the second metal interconnect being disposed at a (N+2)th metal layer and stacked over the plurality of first metal interconnects, the second metal interconnect being electrically coupled to the plurality of first metal interconnects, the second metal interconnect forming the equivalent tapping point of the pin of the first cell block;
planning a semiconductor device according to the standard cell layouts in a cell layout library;
forming a routing pattern to the standard cell layouts;
performing a design rule check (DRC) or a signal electromagnetic simulation test on the routing pattern;
identifying at least one of the standard cell

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Yi-Lin
• Chen Huang-Yu
• Lee Yun-Han

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/396

  Clock trees · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F2217/62

  Physics · mapped topic