Integrated circuit memory devices with customizable standard cell logic

Patent metadata

Field	Value
Publication number	US-10162771-B2
Application number	US-201615346342-A
Country	US
Kind code	B2
Filing date	Nov 8, 2016
Priority date	Nov 9, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a memory cell array; a standard cell region in which first type standard cells implemented to perform a first operation for accessing the memory cell array and second type standard cells performing the first operation and having performance characteristics different from performance characteristics of the first type standard cells are arranged; and a ROM including a program that performs place and route for the standard cells arranged in the standard cell region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a memory cell array;
a standard cell region in which first type standard cells implemented to perform a first operation for accessing the memory cell array and second type standard cells performing the first operation and having performance characteristics different from performance characteristics of the first type standard cells are arranged; and
a ROM including a program that performs place and route for the standard cells arranged in the standard cell region.

2. The semiconductor device of claim 1 , wherein the second type standard cells have latency characteristics different from latency characteristics of the first type standard cells.

3. The semiconductor device of claim 1 , wherein the second type standard cells have operating speed characteristics different from operating speed characteristics of the first type standard cells.

4. The semiconductor device of claim 1 , wherein the second type standard cells have power consumption characteristics different from power consumption characteristics of the first type standard cells.

5. The semiconductor device of claim 1 , further comprising:
first I/O pins; and
I/O pin standard cells determining the number of active pins among the first I/O pins.

6. The semiconductor device of claim 5 , wherein the I/O pin standard cells comprise the first I/O pin standard cell and the second I/O pin standard cell, and
the first I/O pin standard cell and the second I/O pin standard cell determine the different numbers of the active pins from each other.

7. The semiconductor device of claim 1 , wherein the memory cell array comprises a plurality of banks, and
the standard cell region further includes a memory bank standard cell that determines the number of active banks among the plurality of banks.

8. The semiconductor device of claim 7 , wherein the memory bank standard cell comprises a first memory bank standard cell and a second memory bank standard cell, and
the first memory bank standard cell and the second memory bank standard cell determine the different numbers of the active banks from each other.

9. The semiconductor device of claim 1 , wherein the standard cell region further comprises standard cells implemented to perform a second operation for accessing the memory cell array, and
the program defines an operational path of the semiconductor device through performing of the place and route for any one of the first type standard cells and the second type standard cells and the standard cells implemented to perform the second operation.

10. The semiconductor device of claim 1 , further comprising second I/O pins electrically connecting the ROM to an external device of the semiconductor device and making the program transmitted from the external device to the ROM.

11. The semiconductor device of claim 1 , further comprising a DRAM.

12. A semiconductor device comprising:
a memory cell array;
a standard cell region in which first type standard cells defining a critical operational path for accessing the memory cell array and second type standard cells defining a user defined operational path for accessing the memory cell array are arranged; and
a ROM including a program that performs place and route for the standard cells arranged in the standard cell region.

13. The semiconductor device of claim 12 , wherein the second type standard cell performs an operation defined by a user.

14. The semiconductor device of claim 12 , further comprising:
first I/O pins; and
I/O pin standard cells determining the number of active pins among the first I/O pins.

15. The semiconductor device of claim 12 , wherein the memory cell array comprises a plurality of banks, and
the standard cell region further includes a memory bank standard cell that determines the number of active banks among the plurality of banks.

16. The semiconductor device of claim 12 , wherein the standard cell region further comprises standard cells implemented to perform an additional operation for accessing the memory cell array, and
the program defines an operational path of the semiconductor device through performing of the place and route for any one of the first type standard cells and the second type standard cells and the standard cells implemented to perform the additional operation.

17. The semiconductor device of claim 12 , further comprising second I/O pins electrically connecting the ROM to an external device of the semiconductor device and making the program transmitted from the external device to the ROM.

18. An integrated circuit device, comprising:
a memory cell array in a semiconductor substrate;
standard cell logic electrically coupled to said memory cell array, said standard cell logic comprising a first plurality of standard cells configured to support a first operational path for accessing said memory cell array and a second plurality of standard cells configured to support a second user-programmable operational path for accessing said memory cell array; and
a programmable read-only memory (PROM) electrically coupled to said standard cell logic and configured to support a program of instructions that specifies the user-programmable operational path.

19. The device of claim 18 , wherein the PROM is further configured to support a program of operations to be performed by said standard cell logic, which is selected from a group consisting of memory copy, pop count and auto read modify write operations.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jin-Hyun
• Song Won-Hyung

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title