Hypervisor assisted control of CPU access to externally managed physical memory

Patent metadata

Field	Value
Publication number	US-10162665-B1
Application number	US-201615214822-A
Country	US
Kind code	B1
Filing date	Jul 20, 2016
Priority date	Aug 3, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A memory management module receives a request to access a page in a memory, sends the request to a memory controller controlling the memory if the page is available in the memory, and if the page is unavailable, (i) does not send the request to the memory controller, and (ii) generates a first exception. A hypervisor intercepts the first exception and sends a second exception to an operating system. The operating system includes a handler to, in response to the second exception, selectively request the memory controller to obtain the page from a storage device into the memory, and to suspend execution of a first thread issuing the request on a processor until the page becomes available in the memory; and a kernel to schedule execution of a second thread on the processor until the page becomes available, or to idle the processor until the page becomes available.

First claim

What is claimed is:

1. A system comprising:
a memory management module to
receive a request to access a page in a memory,
in response to the page being available in the memory, send the request to a memory controller controlling the memory, and
in response to the page being unavailable in the memory, (i) not send the request to the memory controller, and (ii) generate a first exception, and

a hypervisor to intercept the first exception and send a second exception to an operating system,
wherein the operating system includes
a handler to
in response to the second exception, selectively request the memory controller to obtain the page from a storage device into the memory, and
suspend execution of a first thread issuing the request on a processor until the page becomes available in the memory; and

a kernel to
schedule execution of a second thread on the processor until the page becomes available, or
idle the processor until the page becomes available;

wherein:
the memory controller is further to generate an interrupt prior to evicting a second page from the memory to the storage device;
in response to the interrupt, the kernel is further to generate a hypervisor call;
in response to the hypervisor call, prior to the second page becoming unavailable, the hypervisor is further to:
update status of the second page as being unavailable; and
clean a cache of the processor to obviate access to the second page after the second page becomes unavailable.

2. The system of claim 1 , wherein:
in response to the page becoming available in the memory, the memory controller is further to generate a second interrupt;
in response to the second interrupt, the kernel is further to generate a second hypervisor call;
in response to the second hypervisor call, the hypervisor is further to update status of the page as being available; and
in response to the updated status of the page indicating the page is available,
the kernel is further to resume execution of the first thread issuing the request; and
the memory management module is further to send the request to the memory controller.

3. The system of claim 1 , wherein the handler is further to:
request the memory controller to obtain the page from the storage device into the memory in response to the page storing valid data; and
not request the memory controller to obtain the page from the storage device into the memory in response to the page storing irrelevant data.

4. The system of claim 3 , wherein in response to the page storing irrelevant data, the memory controller is further to make the page available by populating the page with null data.

5. The system of claim 1 , wherein in response to the memory management module deallocating a third page, the hypervisor is further to designate the third page (i) as being unavailable and (ii) as storing data not in use.

6. The system of claim 5 , wherein in response to the hypervisor designating the second page as storing data not in use, the memory controller is further to not evict the second page from the memory to the storage device.

7. A method comprising:
receiving, by a memory management module, a request to access a page in a memory;
sending, by the memory management module, the request to a memory controller controlling the memory in response to the page being available in the memory;
in response to the page being unavailable in the memory, (i) not sending, by the memory management module, the request to the memory controller and (ii) generating, by the memory management module, a first exception;
intercepting, by a hypervisor, the first exception and sending, by the hypervisor, a second exception from the hypervisor to an operating system;
in response to the second exception, selectively requesting, by a handler of an operating system, the memory controller to obtain the page from a storage device into the memory and suspending, by the handler, execution of a first thread issuing the request on a processor until the page becomes available in the memory;
scheduling, by a kernel of the operating system, execution of a second thread on the processor until the page becomes available or idling, by the kernel, the processor until the page becomes available;
generating, by the memory controller, an interrupt prior to evicting a second page from the memory to the storage device;
generating, by the kernel, a hypervisor call in response to the interrupt; and
in response to the hypervisor call, prior to the second page becoming unavailable, updating, by the hypervisor, status of the second page as being unavailable and cleaning, by the hypervisor, a cache of the processor to obviate access to the second page after the second page becomes unavailable.

8. The method of claim 7 , further comprising:
generating, by the memory controller, a second interrupt in response to the page becoming available in the memory;
generating, by the kernel, a second hypervisor call in response to the second interrupt;
updating, by the hypervisor, status of the page as being available in response to the second hypervisor call; and
in response to the updated status of the page indicating the page is available, resuming, by the kernel, execution of the first thread issuing the request and sending, by the memory management module, the request to the memory controller.

9. The method of claim 7 , further comprising:
requesting, by the handler, the memory controller to obtain the page from the storage device into the memory in response to the page storing valid data; and
not requesting, by the handler, the memory controller to obtain the page from the storage device into the memory in response to the page storing irrelevant data.

10. The method of claim 9 , further comprising making, by the memory controller, the page available by populating the page with null data in response to the page storing irrelevant data.

11. The method of claim 7 , further comprising designating, by the hypervisor, in response to the memory management module deallocating a third page, the third page (i) as being unavailable and (ii) as storing data not in use.

12. The method of claim 11 , further comprising:
in response to designating, by the hypervisor, the second page as storing data not in use, not evicting, by the memory controller, the second page from the memory to the storage device.

Assignees

• Marvell Int Ltd

Inventors

• Eidelman Anton

Classifications

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title