Method for manufacturing mirrors with semiconductor saturable absorber

US10162246B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10162246-B2
Application numberUS-201515112567-A
CountryUS
Kind codeB2
Filing dateJan 19, 2015
Priority dateJan 20, 2014
Publication dateDec 25, 2018
Grant dateDec 25, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The invention relates to a method for manufacturing mirrors with saturable semiconducting absorptive material, which includes: depositing a saturable semiconducting absorptive material ( 205 ) onto a growth substrate ( 200 ) in order to form a structure; depositing at least one metal layer onto the structure such as to form a first mirror ( 211 ); and depositing a heat-conductive substrate ( 212 ) onto the metal layer by electrodeposition through an electrically insulating mask ( 312 ), allowing the selective deposition of the thermally conductive substrate, in order to predefine the perimeter of the mirrors with saturable semiconducting absorptive material.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for manufacturing mirrors with semiconductor saturable absorber comprising: the deposition onto a substrate for growth of a semiconductor saturable absorptive material so as to form a structure; the deposition of at least one metal layer onto the structure in order to form a first mirror; the deposition by electro-deposition through an electrically-insulating mask of a thermally-conductive substrate onto the metal layer, allowing the selective deposition of the thermally-conductive substrate, in order for the mask to predefine the perimeter of the mirrors with semiconductor saturable absorber. 2. The method as claimed in claim 1 , comprising a step for introduction of crystal defects into the semiconductor saturable absorptive material in order to limit the lifetime of the carriers in the semiconductor saturable absorptive material to 100 ps. 3. The method as claimed in claim 2 , wherein the step for introduction of crystal defects comprises a step for ion irradiation in the saturable absorptive material. 4. The method as claimed in claim 1 , wherein the first mirror is used as a cathode for the electro-deposition. 5. The method as claimed in claim 1 , wherein the electrically-insulating mask has structure-forming patterns comprising insulating regions and open areas, in order to predefine the perimeter of the mirrors with semiconductor saturable absorber. 6. The method as claimed in claim 1 , further comprising a step for deposition of a second mirror onto the saturable absorptive material. 7. The method as claimed in claim 6 , further comprising a step for deposition of a first phase layer between the first mirror and the saturable absorptive material and a step for deposition of a second phase layer between the second mirror and the saturable absorptive material. 8. The method as claimed in claim 1 , further comprising a step for separation of the mirrors with semiconductor saturable absorber predefined by the mask.

Assignees

Inventors

Classifications

  • In×P and alloy · CPC title

  • Conductive cooling, e.g. by heat sinks or thermo-electric elements · CPC title

  • using intracavity saturable absorbers · CPC title

  • G02F1/3556Primary

    Semiconductor materials, e.g. quantum wells · CPC title

  • Ga×As and alloy · CPC title

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What does patent US10162246B2 cover?
The invention relates to a method for manufacturing mirrors with saturable semiconducting absorptive material, which includes: depositing a saturable semiconducting absorptive material ( 205 ) onto a growth substrate ( 200 ) in order to form a structure; depositing at least one metal layer onto the structure such as to form a first mirror ( 211 ); and depositing a heat-conductive substrate ( 21…
Who is the assignee on this patent?
Centre National De La Rech Scientifique—Cnrs
What technology area does this patent fall under?
Primary CPC classification G02F1/3556. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 25 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).