Small wafer are MEMS switch

Patent metadata

Field	Value
Publication number	US-10160634-B2
Application number	US-201715650953-A
Country	US
Kind code	B2
Filing date	Jul 16, 2017
Priority date	Dec 15, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

First claim

What I claim and desire to protect by Letters Patent is:

1. The process for making a small wafer area MEMS switch comprising:
a silicon wafer having an upper surface and a lower surface,
on said upper surface of said silicon wafer, etching a plurality of separately aligned high aspect ratio closely spaced trenches in said upper surface using a DRIE etch;
growing a lining of thermal oxide in each of said trenches such that each said trench is connected by said lining of thermal oxide wherein said thermal oxide surrounding each said trench blends together in the space between said trenches;
connecting one or more of said trenches with said thermal oxide to form an outer group and enveloping a trench with said thermal oxide, forming an inner group;
filling said trenches with CVD tungsten;
depositing a dielectric layer on said upper silicon wafer surface covering an area between said inner group and said outer group that is not covered with said thermal oxide;
etching a cavity up from said lower surface of and within said silicon wafer surface in vertical alignment with said inner group on said upper surface of said silicon wafer to leave said inner group as a free-standing beam cantilevered at said dielectric layer such that the combination of said free standing beam, said groups and said tungsten elements are adapted to form a MEMS electrical switch;
applying a layer of an electrically conductive outer layer onto a seeded surface within said wafer to form at least one drive electrode, said drive electrode positioned adjacent to and in a plane parallel to said deflection electrode and said stationary electrode;
providing a gap separating a contact point on said deflection electrode from a contact point on said stationary electrode, said contact point on said deflection electrode and said contact point on said stationary electrode each being covered with an insulation material;
said deflection electrode being configured to be electrostatically attracted toward said drive electrode with a cantilevered motion, when said drive electrode is electrically biased, with the result that said insulated contact point on said conductive layer of said deflection electrode makes contact with said insulated contact point on said conductive layer of said stationary electrode.

2. The process for making small wafer area MEMS switch defined in claim 1 comprising:
on said upper surface of said silicon wafer, etching three separately aligned high aspect ratio closely spaced trenches in a first row, in a second row and in a third row using a DRIE etch;
growing a lining of thermal oxide in each of said trenches in said first row, said second row and said third row such that each said trench in said first row, said second row and said third row is connected by said lining of thermal oxide wherein said thermal oxide that surrounds each said trench blends together in the space between said trenches;
said first row of trenches with said thermal oxide connecting same together and said third row of trenches with said thermal oxide connecting same together form an outer group;
said second row of trenches with said thermal oxide, located between said first row of trenches and said third row of trenches forms an inner group;
filling said trenches in said first row, said second row and said third row with CVD tungsten;
depositing a dielectric layer on said upper silicon wafer surface covering an area between said inner group and said outer group that is not covered with said thermal oxide;
etching a cavity up from said lower surface of and within said silicon wafer surface in vertical alignment with said inner group on said upper surface of said silicon wafer to leave said inner group as a free-standing beam cantilevered at said dielectric layer such that the combination of said free standing beam, said loop and said tungsten elements are adapted to form a MEMS electrical switch;
applying a layer of an electrically conductive outer layer onto a seeded surface within said wafer to form at least one drive electrode, said drive electrode positioned adjacent to and in a plane parallel to said deflection electrode and said stationary electrode;
providing a gap separating a contact point on said deflection electrode from a contact point on said stationary electrode, said contact point on said deflection electrode and said contact point on said stationary electrode each being covered with an insulation material;
said deflection electrode being configured to be electrostatically attracted toward said drive electrode with a cantilevered motion, when said drive electrode is electrically biased, with the result that said insulated contact point on said conductive layer of said deflection electrode makes contact with said insulated contact point on said conductive layer of said stationary electrode.

3. The process for making small wafer area MEMS switch defined in claim 2 wherein an interconnect wiring system is formed within said wafer comprising the following dual damascene steps:
using CVD or TEOS depositing an oxide that is the dielectric surrounding the wires;
applying a photoresist, then photopatterning for the trenches for the wires;
RIE said trenches, then clear said resist;
applying a photoresist, then photopatterning for vias for wiring to a layer below;
RIE vias clear the resist;
applying a Ta/TaN blanket film seed plus sputtered Cu seed;
electroplating blanket copper to overfill said trenches;
CMP copper to remove all copper not in etched regions;
RIE to remove Ta/TaN seed where not covered by Cu;
cap with SiN or SiCOH blanket.

4. The process for making the small wafer area MEMS switch defined in claim 3 wherein said blanket seed film is 100 Å to about 1000 Å blanket seed film and 500 Å to about 1000 Å sputtered copper, and said cap has a thickness of between about 100 Å and 1000 Å.

5. The process for making a MEMS switch defined in claim 3 wherein a XeF 2 is used to remove polysilicon in said cavity leaving the seed layer free standing where is contacts said dielectric oxide layer.

6. The process for making a MEMS switch defined in claim 3 wherein said dielectric oxide layer is a compound selected from the group consisting of SiO 2 , Si 3 N 4 and Si x N y .

7. The process for making small wafer area MEMS switch defined in claim 2 wherein an interconnect wiring system is formed within said wafer comprising single damascene steps comprising:
depositing a dielectric layer,
etching a trench;
depositing a barrier liner layer on said etched trenches;
depositing a seed layer on said barrier liner layer;
electroplating a copper fill layer on said feed layer;
CMP copper to remove excess copper not in etched regions;
remove Ta/TaN seed issuing RIE where not covered by copper;
cap with SiN or SiCOH blanket.

8. A process for making a small wafer area MEMS switch comprising:
etching a cavity in a silicon wafer using a DRIE etch to form an interior cavity having a surrounding side wall surface a top and a bottom, and forming within said cavity a freestanding pillar which is a cantilevered beam structure attached at said bottom of said cavity;
depositing and growing on said surface and said contained structure a dielectric oxide layer;
depositing and substantially filling said cavity with polysilicon, to substantially obtain a flat surface at said top of said cavity;
applying photopatterning with photoresist and RIE, etching a plurality of trenches in said deposited polysilicon, said trenches to be used for wiring connections to said MEMS switch;
removing said silicon with DRIE;
removing said photoresist;
depositing a blanket seed layer;
using a wet etch process, remove polysilicon in said cavity leave the seed layer free standing where it

Assignees

• IBM

Inventors

• Webb Bucknell C

Classifications

• B81B2203/04

  Electrodes · CPC title

• B81C2201/0178

  Oxidation · CPC title

• B81B2207/07

  Interconnects · CPC title

• B81B2201/012

  characterised by the shape · CPC title

• B81B2203/0315

  Cavities · CPC title