System and method for providing an Ethernet interface

Patent metadata

Field	Value
Publication number	US-10158686-B2
Application number	US-201614995544-A
Country	US
Kind code	B2
Filing date	Jan 14, 2016
Priority date	Dec 11, 2006
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

In more particular embodiments, v>=n>=m. The communication media interfaces can be electrical and optical. Each of the communication channels can include a SerDes interface operating at least 5 Gigabits per second. Furthermore, each of the m communication media interfaces is configured to transmit a different stream of information over a single optical fiber.

First claim

What is claimed is:

1. A system, comprising:
one or more receivers configured to receive a first information stream;
one or more encoding modules configured to transform the first information stream into a plurality of data blocks; and
one or more muxes configured to multiplex the plurality of data blocks of the first information stream onto a plurality of communication channels using one or more alignment blocks indicating alignments of the plurality of data blocks within the first information stream, wherein:
each of the one or more alignment blocks identifies a virtual lane on which the respective alignment block is placed;
each of the one or more alignment blocks is stored in a virtual lane buffer;
each virtual lane buffer is sized based on an amount of skew expected from electrical and optical components; and
the size of each virtual lane buffer is determined prior to the electrical and optical components generating skew.

2. The system of claim 1 , wherein multiplexing the plurality of data blocks of the first information stream onto a plurality of communication channels using one or more alignment blocks comprises distributing the data blocks onto the plurality of communication channels round robin.

3. The system of claim 2 , wherein the one or more muxes is further configured to insert the alignment blocks onto the plurality of communication channels periodically.

4. The system of claim 1 , wherein each alignment block comprises 66 bits of data.

5. The system of claim 1 , wherein each data block comprises 66 bits of data.

6. The system of claim 1 , wherein:
the one or more receivers are further configured to: receive, from the plurality of communication channels, a second information stream comprising a plurality of data blocks and one or more alignment blocks; and
the one or more muxes are configured to de-multiplex the data blocks of the second information stream using the one or more alignment blocks of the second information stream.

7. The system of claim 1 , wherein the first information stream comprises an aggregate of a plurality of frame streams.

8. The system of claim 7 , wherein the first information stream has a data rate of 100 gigabits per second (“Gbps”), and each of the plurality of frame streams has a data rate less than 100 Gbps.

9. The system of claim 1 , wherein the expected skew from the electrical and optical components is based at least in part on the expected skew from a Tx 100 G Ten Bit Interface (“CTBI”), a Tx optical module, an Rx optical module, and an Rx CTBI.

10. A method, comprising:
receiving a first information stream;
transforming the first information stream into a plurality of data blocks; and
multiplexing the plurality of data blocks of the first information stream onto a plurality of communication channels using one or more alignment blocks indicating alignments of the plurality of data blocks within the first information stream, wherein:
each of the one or more alignment blocks identifies a virtual lane on which the respective alignment block is placed;
each of the one or more alignment blocks is stored in a virtual lane buffer;
each virtual lane buffer is sized based on an amount of skew expected from electrical and optical components; and
the size of each virtual lane buffer is determined prior to the electrical and optical components generating skew.

11. The method of claim 10 , wherein multiplexing the plurality of data blocks of the first information stream onto a plurality of communication channels using one or more alignment blocks comprises distributing the data blocks onto the plurality of communication channels round robin.

12. The method of claim 11 , further comprising inserting the alignment blocks onto the plurality of communication channels periodically.

13. The method of claim 10 , wherein each alignment block comprises 66 bits of data.

14. The method of claim 10 , wherein each data block comprises 66 bits of data.

15. The method of claim 10 , further comprising:
receiving, from the plurality of communication channels, a second information stream comprising a plurality of data blocks and one or more alignment blocks; and
de-multiplexing the data blocks of the second information stream using the one or more alignment blocks of the second information stream.

16. The method of claim 10 , wherein the first information stream comprises an aggregate of a plurality of frame streams.

17. The method of claim 16 , wherein the first information stream has a data rate of 100 gigabits per second (“Gbps”), and each of the plurality of frame streams has a data rate less than 100 Gbps.

18. A non-transitory computer storage readable medium including computer code such that the code is operable, when executed, to:
receive a first information stream;
transform the first information stream into a plurality of data blocks; and
multiplex the plurality of data blocks of the first information stream onto a plurality of communication channels using one or more alignment blocks indicating alignments of the plurality of data blocks within the first information stream, wherein:
each of the one or more alignment blocks identifies a virtual lane on which the respective alignment block is placed;
each of the one or more alignment blocks is stored in a virtual lane buffer;
each virtual lane buffer is sized based on an amount of skew expected from electrical and optical components; and
the size of each virtual lane buffer is determined prior to the electrical and optical components generating skew.

19. The medium of claim 18 , wherein multiplexing the plurality of data blocks onto a plurality of communication channels using one or more alignment blocks comprises distributing the data blocks onto the plurality of communication channels round robin.

20. The medium of claim 19 , wherein the code is further operable, when executed, to insert the alignment blocks onto the plurality of communication channels periodically.

21. The medium of claim 18 , wherein each alignment block comprises 66 bits of data.

22. The medium of claim 18 , wherein each data block comprises 66 bits of data.

23. The medium of claim 18 , wherein the code is further operable, when executed, to:
receive, from the plurality of communication channels, a second information stream comprising a plurality of data blocks and one or more alignment blocks; and
de-multiplex the data blocks of the second information stream using the one or more alignment blocks of the second information stream.

24. The medium of claim 18 , wherein the first information stream comprises an aggregate of a plurality of frame streams.

25. The medium of claim 24 , wherein the first information stream has a data rate of 100 gigabits per second (“Gbps”), and each of the plurality of frame streams has a data rate less than 100 Gbps.

Assignees

• Cisco Tech Inc

Inventors

• Gustlin Mark A
• Trainin Oded
• Della Chiesa Luca

Classifications

• H04L47/10

  Flow control; Congestion control · CPC title

• H04L49/352

  Gigabit ethernet switching [GBPS] · CPC title

• H04L47/39

  Credit based · CPC title

• H04L47/13 Primary

  in a LAN segment, e.g. ring or bus · CPC title

• H04B10/516

  Details of coding or modulation · CPC title