Gated CDS integrator

Patent metadata

Field	Value
Publication number	US-10158335-B2
Application number	US-201615277223-A
Country	US
Kind code	B2
Filing date	Sep 27, 2016
Priority date	Apr 2, 2015
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A Gated CDS Integrator (GCI) may amplify low-level signals without introducing excessive offset and noise. The GCI may also amplify the low level signals with accurate and variable gain. The GCI may include a modulator preceding an amplifier such that offset or noise present in a signal path between the modulator and a demodulator input is translated to a higher out of band frequency, and thereafter reduced by a double sampled discrete time integrator which also reduces thermal noise. The thermal noise may also be reduced by averaging the output of the discrete time integrator.

First claim

We claim:

1. An apparatus, comprising: a modulator having an output to yield a modulator output; an amplifier having an input connected to the modulator output, the amplifier having an amplifier output; and a discrete time integrator connected to the amplifier output and configured to double sample and demodulate the amplifier output to yield a double sampled/demodulated result, wherein the discrete time integrator performs auto-zero functions before integrating the double sampled/demodulated result.

2. The apparatus of claim 1 , wherein the modulator alternately selects one of two inputs, an information bearing signal and either its inverse or a reference signal as the output under a control of a clock synchronized to a clock of the discrete time integrator.

3. The apparatus of claim 1 , wherein the amplifier incorporates a local auto-zero function which auto-zeros an offset and 1/f noise of the amplifier either continuously or periodically.

4. The apparatus of claim 1 , wherein the discrete time integrator integrates the amplifier output for a pre-programmed number of cycles.

5. The apparatus of claim 4 , wherein the discrete time integrator incorporates a lossy element to reduce thermal noise and limit gain.

6. The apparatus of claim 5 , wherein the lossy element comprises one or more of a switch, a capacitor and a timing circuit.

7. The apparatus of claim 4 , wherein after the pre-programmed number of cycles, the discrete time integrator is placed in a hold mode.

8. The apparatus of claim 1 , wherein the discrete time integrator incorporates a local auto-zero function which is synchronized to a clock of the discrete time integrator.

9. The apparatus of claim 8 , further comprising a digitizer which converts the double sampled/demodulated result from an analog signal to a digital word or bit stream.

10. The apparatus of claim 9 , wherein the local auto-zero function is refreshed while the digitizer processes a held double sampled/demodulated result.

11. The apparatus of claim 9 , wherein the digitizer receives outputs from a plurality of discrete time integrators.

12. The apparatus of claim 1 , wherein a discrete time integrator output of the discrete time integrator has a variable discrete time gain.

13. The apparatus of claim 12 , wherein the variable discrete time gain is controlled by one or more of a comparator, a counter, a register and non-overlapping clock circuitry.

14. The apparatus of claim 1 , wherein the auto-zero functions are local, variable and adapt to varying offsets in the amplifier or integrator.

15. A gated correlated double sampling integrator, comprising: a modulator; one or more auto-zero functions; a double sampler; and a discrete time lossy integrator, and a digitizer which converts an analog output to a digital output wherein signal processing of a signal via the modulator, the one or more auto-zero functions, the double sampler and the discrete time lossy integrator reduce at least one of offset, 1/f and thermal noise present in a signal path of the signal and one or more auto-zero functions are refreshed while the digitizer processes a held analog output.

16. The gated correlated double sampling integrator of claim 15 , configured to operate in a high total ionizing dose environment where a cumulative dose can exceed 1 Mrad (Si).

17. The gated correlated double sampling integrator of claim 15 , configured to integrate at least one of offset, 1/f and thermal noise present in the signal path for a pre-programmed number of cycles.

18. A system comprising: a modulator that receives and processes a signal, to yield a modulated signal; an amplifier that receives and processes the modulated signal and having auto-zeroed its own offset and 1/f noise, to yield an amplified signal; a switched capacitor double sampler that demodulates the amplified signal to yield a demodulated signal; a switched capacitor lossy integrator that auto-zeros its offset and integrates the demodulated signal to yield an integrated signal; and a digitizer that converts the integrated signal from analog to digital.

Assignees

• Nasa

Inventors

• Quilligan Gerard T
• Aslam Shahid

Classifications

• H03F1/26

  Modifications of amplifiers to reduce influence of noise generated by amplifying elements · CPC title

• H03F3/387 Primary

  with semiconductor devices only · CPC title

• H03F2203/45288

  Differential amplifier with circuit arrangements to enhance the transconductance · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F3/45596

  by offset reduction · CPC title