CMOS and bipolar device integration including a tunable capacitor

US10158030B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10158030-B2
Application numberUS-201715431623-A
CountryUS
Kind codeB2
Filing dateFeb 13, 2017
Priority dateFeb 13, 2017
Publication dateDec 18, 2018
Grant dateDec 18, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A tunable capacitor may include a first terminal having a first semiconductor component with a first polarity. The tunable capacitor may also include a second terminal having a second semiconductor component with a second polarity. The second component may be adjacent to the first semiconductor component. The tunable capacitor may further include a first conductive material electrically coupled to a first depletion region at a first sidewall of the first semiconductor component.

First claim

Opening claim text (preview).

What is claimed is: 1. A tunable capacitor, comprising: a first terminal comprising a first semiconductor component with a first polarity; a second terminal comprising a second semiconductor component with a second polarity, adjacent to the first semiconductor component; and a first conductive material electrically coupled to a first depletion region, the first depletion region proximate a first sidewall of the first semiconductor component. 2. The tunable capacitor of claim 1 , further comprising a second conductive material electrically coupled to a second depletion region at a second sidewall of the first semiconductor component. 3. The tunable capacitor of claim 2 , in which the second depletion region extends onto a surface of the second conductive material that faces the second semiconductor component. 4. The tunable capacitor of claim 1 , in which the first semiconductor component comprises a compound semiconductor. 5. The tunable capacitor of claim 4 , in which the first semiconductor component comprises a III-V compound semiconductor material or a II-VI compound semiconductor material. 6. The tunable capacitor of claim 1 , in which the first conductive material comprises a metal stack. 7. The tunable capacitor of claim 1 , in which the first conductive material comprises a Schottky contact. 8. The tunable capacitor of claim 1 , in which the first depletion region extends onto a surface of the first conductive material that faces the second semiconductor component. 9. The tunable capacitor of claim 1 , in which the first semiconductor component comprises an N-type collector, and the second semiconductor component comprises a P-type doped base. 10. The tunable capacitor of claim 1 , integrated into a radio frequency (RF) front end module, the RF front end module incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer. 11. A method of integrating a semiconductor device with a complementary metal-oxide-semiconductor (CMOS) structure, comprising: forming a collector layer, a base layer, and an emitter layer on a semiconductor substrate; patterning the emitter layer; fabricating metallization to access the emitter layer; bonding the CMOS structure to the semiconductor substrate; patterning the collector layer and the base layer to form the semiconductor device; forming vias to access the CMOS structure; and electrically coupling the CMOS structure to the semiconductor device. 12. The method of claim 11 , in which the CMOS structure comprises a CMOS capacitor and the semiconductor device comprises a heterojunction bipolar transistor (HBT) and/or a tunable capacitor. 13. The method of claim 11 , in which the semiconductor device comprises a III-V compound semiconductor material or a II-VI compound semiconductor material. 14. The method of claim 11 , in which the CMOS structure comprises at least one CMOS device. 15. The method of claim 11 , further comprising fabricating at least one conductive bump. 16. The method of claim 11 , in which the semiconductor substrate comprises silicon, gallium arsenide (GaAs), or indium phosphide. 17. The method of claim 11 , further comprising integrating the semiconductor device into a radio frequency (RF) front end module, the RF front end module incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer. 18. A radio frequency (RF) front end module, comprising: a filter, comprising a die, a substrate supporting the die, a molding compound surrounding the die, a tunable capacitor comprising a first terminal comprising a first semiconductor component with a first polarity, a second terminal comprising a second semiconductor component with a second polarity, adjacent to the first semiconductor component, and a first conductive material electrically coupled to a first depletion region at a first sidewall of the first semiconductor component; a diplexer coupled to the filter; and an antenna coupled to an output of the diplexer. 19. The RF front end module of claim 18 , in which the first semiconductor component comprises an N-type collector, and the second semiconductor component comprises a P-type doped base. 20. The RF front end module of claim 18 , incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

Assignees

Inventors

Classifications

  • for antennas · CPC title

  • comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

  • Multilayered bumps, e.g. a coating on top and side surfaces of a bump core · CPC title

  • relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

  • Capacitive arrangements (H10W44/20 takes precedence) · CPC title

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What does patent US10158030B2 cover?
A tunable capacitor may include a first terminal having a first semiconductor component with a first polarity. The tunable capacitor may also include a second terminal having a second semiconductor component with a second polarity. The second component may be adjacent to the first semiconductor component. The tunable capacitor may further include a first conductive material electrically coupled…
Who is the assignee on this patent?
Qualcomm Inc
What technology area does this patent fall under?
Primary CPC classification H01L29/93. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 18 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).