Method of making a graphene base transistor with reduced collector area
US-9590081-B2 · Mar 7, 2017 · US
Method of making a graphene base transistor with reduced collector area
US10158009B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10158009-B2 |
| Application number | US-201715408813-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 18, 2017 |
| Priority date | Mar 20, 2013 |
| Publication date | Dec 18, 2018 |
| Grant date | Dec 18, 2018 |
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Abstract
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A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith.
First claim
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What we claim is: 1. A product of a process of making a graphene base transistor with reduced collector area comprising: forming a graphene material layer with a right and left lateral side portion over the top of a third region right and left side material; forming a collector material on a substrate; depositing a dielectric in the third region right and left side material; planarizing the dielectric in the third region right and left side material; cleaning and removing the native oxide on the top surface of the collector material; transferring a base graphene material layer to the top surface of the graphene material layer; bonding the base graphene material layer; and photostepping and defining a second graphene material layer to the top surface of the graphene material layer. 2. The product of the process of making a graphene base transistor with reduced collector area of claim 1 wherein the graphene is doped and wherein said doping increases the graphene to semiconductor heterojunction harrier height and lowers the base resistance. 3. The product of the process of making a graphene base transistor with reduced collector area of claim 2 further comprising the step of: depositing a material protection layer on the surface of the collector material.
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H01L29/7371Primary
Electricity · mapped topic
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- What does patent US10158009B2 cover?
- A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces the…
- Who is the assignee on this patent?
- Us Navy
- What technology area does this patent fall under?
- Primary CPC classification H01L29/7371. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 18 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).