Self-aligned interconnection for integrated circuits

Patent metadata

Field	Value
Publication number	US-10157788-B2
Application number	US-201615000935-A
Country	US
Kind code	B2
Filing date	Jan 19, 2016
Priority date	Aug 23, 2012
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

First claim

What is claimed is:

1. A method, comprising:
forming semiconductor devices over a substrate;
forming a protective hard mask material to protect the semiconductor devices;
forming a dielectric material over the protective hard mask material;
forming one or more trenches in the dielectric material while using the protective hard mask material to protect the semiconductor devices under the one or more trenches while extending one or more self-aligned contact vias from the one or more trenches to one or more electrode contact regions, wherein extending the one or more self-aligned contact vias comprises exposing one or more word-line contact regions.

2. The method of claim 1 , wherein forming the protective hard mask is performed without a critical mask.

3. The method of claim 1 , further comprising depositing an electrically conductive material in the one or more trenches to form one or more word-line electrodes in the one or more trenches and one or more word-line interconnects in the one or more self-aligned contact vias, the word-line interconnects being in substantially direct contact with the one or more word-line contact regions.

4. The method of claim 3 , wherein extending the one or more self-aligned contact vias comprises exposing buried n+ silicon word-line contact regions.

5. The method of claim 4 , wherein forming semiconductor devices comprises forming a phase change memory array comprising a plurality of phase change memory cells.

6. The method of claim 5 , wherein forming the protective hard mask material comprises forming planar buried hard mask between the dielectric material and the phase change memory array.

7. The method of claim 6 , wherein forming the one or more trenches comprises patterning a plurality of mandrel lines over the planar buried hard mask and forming spacers over sidewalls of the mandrel lines.

8. The method of claim 7 , wherein forming the one or more trenches further comprises utilizing the spacers as masks to pattern the one or more trenches.

9. The method of claim 1 , wherein forming the protective hard mask material comprises depositing an etch stop layer conformally over the semiconductor devices.

10. A method, comprising:
forming semiconductor devices over a substrate;
forming a protective hard mask material to protect the semiconductor devices, wherein forming the protective hard mask material comprises depositing an etch stop layer conformally over the semiconductor devices;
forming a dielectric material over the protective hard mask material;
forming one or more trenches in the dielectric material while using the protective hard mask material to protect the semiconductor devices under the one or more trenches while extending one or more self-aligned contact vias from the one or more trenches to one or more electrode contact regions;
wherein forming the semiconductor devices comprises:
forming additional hard mask elements on a plurality of bit-line stacks each comprising a bit-line electrode, a bit-line connector, and a phase change storage material; and
patterning the bit-line stacks using the hard mask elements.

11. The method of claim 10 , wherein forming the one or more trenches further comprises etching the etch stop layer to expose word-line electrode contact regions and the additional hard mask elements of the bit-line stacks.

12. A method of fabricating an integrated circuit, comprising:
forming a hard mask over a first insulating layer, the hard mask including an elongate slot;
forming a second insulating layer over the hard mask; and
etching a plurality of trenches in the second insulating layer, the trenches intersecting the elongate slot at intersections, wherein etching the plurality of trenches comprises extending a plurality of contacts vias from the intersections of the trenches through the elongate slot and through the first insulating layer.

13. The method of claim 12 , further comprising a pitch-multiplication masking process to define a trench mask, wherein etching the plurality of trenches comprises etching through the trench mask.

14. The method of claim 13 , wherein the pitch-multiplication masking process comprises defining mandrel mask lines by lithography, depositing sidewall spacers on the mandrel mask lines, and removing the mandrel mask lines from between the sidewall spacers.

15. The method of claim 12 , further comprising defining the elongate slot with a non-critical mask.

16. The method of claim 12 , wherein the second insulating layer comprises a conductive line.

17. The method of claim 16 , wherein the conductive line contacts the elongate slot at one of the intersections.

18. The method of claim 12 , wherein the second insulating layer comprises an electrode line and the first insulating layer comprises a contact.

Assignees

• Micron Technology Inc

Inventors

• Pellizzer Fabio
• Rigano Antonino
• Somaschini Roberto

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/086

  involving buried masks · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title