Booster circuit and non-volatile memory including the same

Patent metadata

Field	Value
Publication number	US-10157645-B2
Application number	US-201715784330-A
Country	US
Kind code	B2
Filing date	Oct 16, 2017
Priority date	Nov 22, 2016
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

To obtain a booster circuit capable of reducing voltage stress applied to a booster cell, provided is a booster circuit including a plurality of booster cells connected in series. Each of the plurality of booster cells includes a charge transfer transistor connected between an input terminal and an output terminal, and a boost capacitor connected between the input terminal and a clock terminal. Among the plurality of booster cells, a plurality of booster cells at least in a last stage are connected in parallel so that the plurality of booster cells connected in parallel are connected to a booster cell in a previous stage of the last stage by switching the plurality of booster cells in the last stage in accordance with a boosting operation.

First claim

What is claimed is:

1. A booster circuit, comprising:
first booster cells; and
two second booster cells, the first booster cells each comprising:
a first charge transfer transistor connected between a first input terminal and a first output terminal; and
a boost capacitor connected between the first input terminal and a clock terminal,
the two second booster cells each comprising:
a second charge transfer transistor, in which one terminal of a first switching element is connected to a second input terminal and a control terminal of the first switching element is connected to an enable terminal, the second charge transfer transistor being connected between another terminal of the first switching element and a second output terminal;
a second boost capacitor having one terminal connected to the another terminal of the first switching element; and
a second switching element in which the enable terminal is connected to a control terminal of the second switching element. the second switching element being connected between a clock terminal and another terminal of the second boost capacitor,
the first booster cells being connected in series in a first stage to a previous stage of a last stage,
the two second booster cells being connected in parallel in the last stage, and
the booster circuit having a function to turn on one of the two second booster cells and turn off another one of the two second booster cells in accordance with a boosting operation.

2. A booster circuit according to claim 1 , further comprising a level shift circuit configured to convert a signal level of an input to the enable terminal of each of the two second booster cells into a level of a voltage at the first input terminal of the first booster cell in the previous stage of the last stage.

3. A non-volatile memory, comprising the booster circuit of claim 1 .

4. A non-volatile memory, comprising the booster circuit of claim 2 .

Assignees

• Sii Semiconductor Corp
• Ablic Inc

Inventors

• Mitani Makoto

Classifications

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• H02M2003/078

  Electricity · mapped topic

• G11C16/30

  Power supply circuits · CPC title

• G11C5/145 Primary

  Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence) · CPC title