Operating system-managed interrupt steering in multiprocessor systems

Patent metadata

Field	Value
Publication number	US-10157155-B2
Application number	US-201615241104-A
Country	US
Kind code	B2
Filing date	Aug 19, 2016
Priority date	Jun 13, 2013
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

An operating system includes an interrupt router that dynamically steers each interrupt to one or more processors within set of processors based on overall load information from the set of processors. An interrupt source is assigned to a processor based on the load imposed by the interrupt source and the target overall load for the processor. For example, each processor can maintain information about each interrupt it processes over time. The operating system receives this historical load information to determine an expected load for interrupts of a given type from a given device, an overall load on the system, and a target load for each processor. Given a set of interrupt sources, their expected loads, and target load for each processor, each interrupt source can be assigned dynamically to a processor during runtime of the system. These assignments can be changed given current operating conditions of the system.

First claim

What is claimed is:

1. A computer-implemented process performed by a computer including a processing device comprising a plurality of processors, comprising:
periodically receiving into a data structure in memory for an interrupt router, from the plurality of processors, data indicating an amount of processing time consumed by the plurality of processors due to executing interrupt handlers;
the interrupt router determining a load on the processing device due to interrupt handling by the plurality of processors based on at least the received data; and
assigning, by the interrupt router, each interrupt source of a plurality of interrupt sources to a selected respective processor from among the plurality of processors, the plurality of interrupt sources having a corresponding plurality of interrupt handlers based on at least a function of the determined load so as to distribute the load among the processors while maximizing a number of processors that are idle; and
repeating determining the load and assigning each interrupt source based on the periodically received data.

2. The computer-implemented process of claim 1 , further comprising:
the interrupt router further periodically receiving and storing, in the data structure, data indicating an amount of processing time consumed by any processes invoked by the interrupt handlers.

3. The computer-implemented process of claim 1 , wherein assigning comprises:
the interrupt router identifying a number of processors, from among the plurality of processors, available for processing interrupts;
the interrupt router selecting a number of processors, from among the identified number of processors available for processing interrupts, such that the number of selected processors matches the determined load divided by a target per-processor load.

4. The computer-implemented process of claim 1 , further comprising: the interrupt router aggregating, by interrupt source, the data received from the plurality of processors.

5. The computer-implemented process of claim 1 , further comprising each processor determining the amount of processing time consumed by the respective processor for executing interrupt handlers by:
storing a system time stamp when beginning execution of the interrupt handler;
computing a difference between a system time stamp observed when ending execution of the interrupt handler; and
storing the computed difference.

6. The computer-implemented process of claim 5 , wherein each processor determining the amount of processing time further comprises:
for any process invoked by the interrupt handler,
storing a system time stamp when beginning execution of the process;
computing a difference between a system time stamp observed when ending execution of the process; and
storing data indicative of the computed difference for the process and the computed difference for the interrupt handler.

7. The computer-implemented process of claim 6 , wherein each processor determining the amount of processing time further comprises:
for any preemptive activity preempting interrupt processing by the interrupt handler and associated processes on the respective processor,
computing a difference between system time stamps observed when pausing the preempted interrupt processing and when restarting the preempted interrupt processing to have an amount of time for executing the preemptive activity; and
wherein the computed difference for the interrupt handler excludes the amount of time for executing the preemptive activity.

8. An article of manufacture comprising:
a computer storage medium comprising at least a memory or a storage device;
computer program instructions stored on the computer storage medium which, when read from storage and processed by a processing device including a plurality of processors, instruct the processing device to perform a process comprising:

periodically receiving into a data structure in memory for an interrupt router, from the plurality of processors, data indicating an amount of processing time consumed by the plurality of processors due to executing interrupt handlers;
the interrupt router determining a load on the processing device due to interrupt handling by the plurality of processors based on at least the received data; and
assigning, by the interrupt router, each interrupt source of a plurality of interrupt sources to a selected respective processor from among the plurality of processors, the plurality of interrupt sources having a corresponding plurality of interrupt handlers based on at least a function of the determined load so as to distribute the load among the processors while maximizing a number of processors that are idle; and
repeating determining the load and assigning each interrupt source based on the periodically received data.

9. The article of manufacture of claim 8 , wherein the process further comprises:
the interrupt router further periodically receiving and storing, in the data structure, data indicating an amount of processing time consumed by any processes invoked by the interrupt handlers.

10. The article of manufacture of claim 8 , wherein assigning comprises:
the interrupt router identifying a number of processors, from among the plurality of processors, available for processing interrupts;
the interrupt router selecting a number of processors, from among the identified number of processors available for processing interrupts, such that the number of selected processors matches the determined load divided by a target per-processor load.

11. The article of manufacture of claim 8 , wherein the process further comprises: the interrupt router aggregating, by interrupt source, the data received from the plurality of processors.

12. The article of manufacture of claim 8 , further comprising each processor determining the amount of processing time consumed by the respective processor for executing interrupt handlers by:
storing a system time stamp when beginning execution of the interrupt handler;
computing a difference between a system time stamp observed when ending execution of the interrupt handler; and
storing the computed difference.

13. The article of manufacture of claim 12 , wherein each processor determining the amount of processing time further comprises:
for any process invoked by the interrupt handler,
storing a system time stamp when beginning execution of the process;
computing a difference between a system time stamp observed when ending execution of the process; and
storing data indicative of the computed difference for the process and the computed difference for the interrupt handler.

14. The article of manufacture of claim 13 , wherein each processor determining the amount of processing time further comprises:
for any preemptive activity preempting interrupt processing by the interrupt handler and associated processes on the respective processor,
computing a difference between system time stamps observed when pausing the preempted interrupt processing and when restarting the preempted interrupt processing to have an amount of time for executing the preemptive activity; and
wherein the computed difference for the interrupt handler excludes the amount of time for executing the preemptive activity.

15. A computer comprising:
a processing device comprising a plurality of processors,
a plurality of interrupt sources, the plurality of interrupt sources having a corresponding plurality of interrupt handlers;
an interrupt router executed on one or more of the plurality of processors, the interrupt router being configured to:
periodically receive, into a data st

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Raffman Andrew
• Kim Minsang
• Wohlgemuth Jason
• Brown Tristan
• Barakat Youssef
• Fatemieh Omid

Classifications

• G06F2201/865

  Monitoring of software · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F9/5083

  Techniques for rebalancing the load in a distributed system · CPC title

• G06F11/3466

  Performance evaluation by tracing or monitoring · CPC title

• G06F2201/835

  Timestamp · CPC title