Memory device and host device

Patent metadata

Field	Value
Publication number	US-10157149-B2
Application number	US-201514956802-A
Country	US
Kind code	B2
Filing date	Dec 2, 2015
Priority date	Dec 2, 2014
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

According to one embodiment, a memory device includes: a nonvolatile semiconductor memory; and a controller which controls the semiconductor memory. The controller includes: a first memory which stores a first key; a second memory which stores a second key; a first generator which generates a third key based on a random number; a second generator which generates a fourth key based on the first key and the third key; and an encryptor which encrypts the second key with the third key. The third key and the encrypted second key are stored in a host device enabled to access the memory device.

First claim

What is claimed is:

1. A memory device comprising:
a nonvolatile semiconductor memory; and
a controller which controls the semiconductor memory, wherein the controller includes:
a first memory which stores a first key, the first memory being a nonvolatile memory;
a second memory which stores a second key, the second memory being a volatile memory;
a first generator which generates a third key based on a random number;
a second generator which generates a fourth key based on the first key and the third key; and
an encryptor which encrypts the second key with the fourth key, wherein

the third key and the encrypted second key are stored in a host device enabled to access the memory device, and
the third key and the encrypted second key are preserved, when a power supply to the memory device is being turned off, by being transmitted from the memory device to the host device.

2. The memory device according to claim 1 , wherein the controller further includes a decryptor,
the second generator generates the fourth key based on the first key and the third key read from the host device, and
the decryptor decrypts the encrypted second key read from the host device based on the fourth key.

3. The memory device according to claim 2 , wherein, when the power supply to the memory device is turned on, the decryptor decrypts the encrypted second key read from the host device.

4. The memory device according to claim 1 , wherein the third key is stored in the semiconductor memory.

5. The memory device according to claim 4 , wherein, when the power supply to the memory device is turned on, the third key read from the host device is compared with the third key read from the semiconductor memory.

6. The memory device according to claim 1 , wherein
the controller further includes a third memory which stores access information on the semiconductor memory, and
the access information is transmitted to the host device before the power supply to the memory device is turned off.

7. The memory device according to claim 6 , wherein the access information is encrypted by the encryptor, and the encrypted access information is stored in the host device.

8. The memory device according to claim 6 , wherein
the controller further includes a third generator which generates a digital signature,
the digital signature is attached to the access information, and
the access information with the digital signature attached thereto is stored in the host device.

9. The memory device according to claim 1 , wherein the third key is a one-time password.

10. The memory device according to claim 1 , wherein, upon receiving a first signal from the host device, the controller allows the encryptor to encrypt the second key and transmits the encrypted second key and the third key to the host device.

11. The memory device according to claim 1 , wherein,
after transmitting the encrypted second key and the third key, the controller transmits information indicating that preparation for power supply shutdown is completed, to the host device, and
in response to the information indicating that preparation for power supply shutdown is completed, the power supply is turned off.

12. The memory device according to claim 1 , wherein data transmitted from a host device is encrypted with the second key.

13. A host device comprising:
a processor; and
a memory, wherein,
when the power supply to a memory device is turned off by the processor, the host device receives an encrypted second key and a third key from the memory device and stores the second and third keys in the memory,
when returning on the power supply to the memory device, the host device transmits the encrypted second key and the third key stored in the memory to the memory device, and
the encrypted second key is generated by encrypting the second key based on the third key and a first key concealed in the memory device.

14. The host device according to claim 13 , wherein, when the processor turns off the power supply, the processor transmits information indicating that the power supply is to be turned off, and receives the encrypted second key and the third key from the memory device in response to the information.

15. The host device according to claim 13 , wherein the host device receives the encrypted second key and the third key and further receives a first signal, and
in response to the first signal, the processor turns off the power supply.

16. The host device according to claim 13 , wherein, when the host device turns off the power supply, the host device receives access information on the memory device and stores the access information in the memory.

17. The host device according to claim 16 , wherein the access information is encrypted, and the encrypted access information is transmitted to the host device.

18. The host device according to claim 16 , wherein a digital signature is attached to the access information, and the access information with the digital signature attached thereto is transmitted to the host device.

19. The host device according to claim 13 , wherein the memory is a volatile memory.

20. The host device according to claim 13 , wherein data transmitted from the host device to the memory is encrypted with the second key.

Assignees

• Toshiba Memory Corp

Inventors

• Nagai Koichi
• Kashiwagi Yuji

Classifications

• H04L63/0457

  wherein the sending and receiving network entities apply dynamic encryption, e.g. stream encryption (cryptographic mechanisms or cryptographic arrangements for stream encryption H04L9/065) · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• H04L63/067

  using one-time keys (cryptographic mechanisms or cryptographic arrangements for generation of one-time passwords H04L9/0863) · CPC title

• H04L63/126

  the source of the received data · CPC title