Multi-core dynamic frequency control system

Patent metadata

Field	Value
Publication number	US-10156882-B2
Application number	US-201514879269-A
Country	US
Kind code	B2
Filing date	Oct 9, 2015
Priority date	Oct 9, 2015
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

First claim

The invention claimed is:

1. A multi-core processor comprising:
a plurality of processor cores;
combinatorial logic that determines which one of the plurality of processor cores controls a system frequency provided to the plurality of processor cores; and
at least a selected one of the plurality of processor cores further comprises:
a programmable voltage regulator that regulates a first core voltage within the selected processor core;
multiplexer logic that provides voltage control codes to the programmable voltage regulator, wherein the voltage control codes are selected by the multiplexer logic from one of a plurality of multiplexer inputs based upon the determination of the combinatorial logic;
critical path monitor logic that collects critical path measurements within the selected processor core; and
voltage control logic that provides the voltage control codes to a first one of the plurality of multiplexer inputs, wherein the voltage control logic generates the voltage control codes based upon the critical path measurements and one or more offset values configured to prevent the first core from taking control of the system frequency.

2. The multi-core processor of claim 1 wherein the controlling of the first core voltage further comprises:
decreasing the first core voltage until the one or more critical path measurements change; and
increasing the first core voltage based on the one or more offset values.

3. The multi-core processor of claim 1 wherein the controlling of the first core voltage further comprises:
increasing the first core voltage based on the one or more offset values in response to determining that the first core voltage does not include a voltage margin.

4. The multi-core processor of claim 1 wherein the programmable voltage regulator controls the first core voltage independent from one or more second voltages corresponding to one or more different cores included in the plurality of cores.

5. An information handling system comprising:
one or more multi-core processors;
a memory coupled to the one or more multi-core processors; and
a set of computer program instructions stored in the memory and executed by at least one of the multi-core processors in order to perform actions of:
determining whether a first core included in a multi-core processor is controlling a system frequency that drives the first core and one or more second cores also included in the multi-core processor; and
in response to determining that the first core is not controlling the system frequency, controlling a first core voltage of the first core using voltage control codes, independent from one or more second voltages of the one or more second cores, based upon one or more critical path measurements within the first core, wherein the voltage control codes are based upon the one or more critical path measurements and one or more offset values configured to prevent the first core from taking control of the system frequency.

6. The information handling system of claim 5 wherein at least one of the one or more multi-core processors perform additional actions comprising:
determining that thermometer code information generated from the one or more critical path measurements does not match frequency control information corresponding to the system frequency.

7. The information handling system of claim 6 wherein at least one of the one or more multi-core processors perform additional actions comprising:
in response to the thermometer code matching the frequency control information, providing pervasive control codes from the multi-core processor to the programmable voltage regulator to control the first core voltage in conjunction with at least one of the one or more second voltages.

8. The information handling system of claim 5 wherein at least one of the one or more multi-core processors perform additional actions comprising:
providing the voltage control codes generated by voltage control logic internal to the first core to a programmable voltage regulator that controls the first core voltage.

9. The information handling system of claim 5 wherein at least one of the one or more multi-core processors perform additional actions comprising:
decreasing the first core voltage until the one or more critical path measurements change; and
increasing the first core voltage based on the one or more offset values.

10. The information handling system of claim 5 wherein at least one of the one or more multi-core processors perform additional actions comprising:
increasing the first core voltage based on the one or more offset values in response to determining that the first core voltage does not include a voltage margin.

Assignees

• IBM

Inventors

• Campisano Francesco A
• Drake Alan J
• Floyd Michael S
• Hui David T
• Owczarczyk Pawel
• Tiner Marshall D
• Yuan Xiaobin

Classifications

• Y02D10/126

  Cross-Sectional Technologies · mapped topic

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title