Low density party check (LDPC) decoder and method of decoding performed by LDPC decoder in digital video broadcasting (DVB) system

Patent metadata

Field	Value
Publication number	US-10153783-B2
Application number	US-201414477177-A
Country	US
Kind code	B2
Filing date	Sep 4, 2014
Priority date	Sep 16, 2013
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A low density parity check (LDPC) decoder, including a memory configured to store a log-likelihood ratio (LLR) value of bits output from a demapper, and an LLR message exchanged between a variable node and an inspection node. The LDPC decoder further includes a node processor configured to select a decoding algorithm from a first algorithm and a second algorithm based on a code rate of an LDPC code, and decode the LLR message based on the selected decoding algorithm.

First claim

What is claimed is:

1. A low density parity check (LDPC) decoder in a digital video broadcasting (DVB) system in a digital video broadcasting (DVB) system, comprising:
a memory configured to store a log-likelihood ratio (LLR) value of bits output from a demapper, and an LLR message exchanged between a variable node and an inspection node; and
a node processor configured to
compare a code rate of an LDPC code to a threshold value,
select a function F(x)-based sum-product decoding algorithm as a decoding algorithm in response to the code rate being less than or equal to the threshold value,
select a min-sum decoding algorithm as the decoding algorithm in response to the code rate being greater than the threshold value, and
decode the LLR message based on the selected decoding algorithm, wherein the node processor comprises one or more decoders configured to
decode the LLR message based on the function F(x)-based sum-product decoding algorithm in response to the function F(x)-based sum-product decoding algorithm being selected,
decode the LLR message based on the min-sum decoding algorithm in response to the min-sum decoding algorithm being selected, and
wherein the one or more decoders are configured to complementarily perform the decoding.

2. The LDPC decoder of claim 1 , wherein a first decoder for the function F(x)-based sum-product decoding algorithm is configured to:
receive a d number of LLR messages;
calculate a sum of function values of the d number of LLR messages;
delay the calculated sum for a d period of time;
subtract, one by one, a function value F(x) of each of the d number of LLR messages from the delayed calculated sum;
calculate F −1 (x) based on a result of the subtraction; and
output a result of the calculation of the F −1 (x) as the d number of LLR messages.

3. The LDPC decoder of claim 1 , wherein a second decoder for the min-sum decoding algorithm is configured to:
receive a d number of LLR messages;
search for a first minimum value and a second minimum value from the d number of LLR messages;
select one of the first minimum value and the second minimum value;
divide the selected minimum value by a first value, or add the selected minimum value to a second value, to update the d number of LLR messages; and
output the updated d number of LLR messages.

4. A method of decoding performed by a low density parity check (LDPC) decoder in a digital video broadcasting (DVB) system, the method comprising:
storing a log-likelihood ratio (LLR) value of bits output from a demapper, and an LLR message exchanged between a variable node and an inspection node;
comparing a code rate to a threshold value;
selecting a function F(x)-based sum-product decoding algorithm as a decoding algorithm in response to the code rate being less than or equal to the threshold value;
selecting a min-sum decoding algorithm as the decoding algorithm in response to the code rate being greater than the threshold value;
decoding, using one or more decoders, the LLR message based on the function F(x)-based sum-product decoding algorithm in response to the function F(x)-based sum-product decoding algorithm being selected; and
decoding, using one or more decoders, the LLR message based on the min-sum decoding algorithm in response to the min-sum decoding algorithm being selected,
wherein the one or more decoders complementarily perform the decoding.

5. The method of claim 4 , wherein the decoding of the LLR message based on the function F(x)-based sum-product decoding algorithm comprises:
receiving a d number of LLR messages;
calculating a sum of function values of the d number of LLR messages;
delaying the calculated sum for a d period of time;
subtracting, one by one, a function value F(x) of each of the d number of LLR messages from the delayed calculated sum;
calculating F −1 (x) based on a result of the subtracting; and
outputting a result of the calculating of the F −1 (x) as the d number of LLR messages.

6. The method of claim 4 , wherein the decoding of the LLR message based on the min-sum decoding algorithm comprises:
receiving a d number of LLR messages;
searching for a first minimum value and a second minimum value from the d number of LLR messages;
selecting one of the first minimum value and the second minimum value;
dividing the selected minimum value by a first value, or adding the selected minimum value to a second value, to update the d number of LLR messages; and
outputting the updated d number of LLR messages.

7. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 4 .

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kyung Gyu Bum
• Shim Jae Wook
• Yang Ho

Classifications

• H03M13/1165 Primary

  QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2] · CPC title

• H03M13/658

  Scaling by multiplication or division · CPC title

• H03M13/6583

  Normalization other than scaling, e.g. by subtraction · CPC title

• H03M13/1125

  using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs · CPC title

• H03M13/3707

  Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code · CPC title