Fractional frequency clock divider with direct division

Patent metadata

Field	Value
Publication number	US-10153777-B2
Application number	US-201615281617-A
Country	US
Kind code	B2
Filing date	Sep 30, 2016
Priority date	Sep 30, 2016
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number NK cycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.

First claim

The following is claimed:

1. A fractional frequency divider (FFD) circuit, comprising:
a dynamic divider circuit to count clock edges of an input clock signal having an input frequency and to provide phase shifted first and second pulse output signals in response to counting of an adjustable integer number N K cycles of the input clock signal, the dynamic divider circuit including:
a first output to provide the first pulse output signal including a first edge and a second edge, the first edge of the first pulse output signal following an Nth edge in a sequence of N K consecutive edges of the input clock signal,
a second output to provide the second pulse output signal including a first edge and a second edge, the first edge of the second pulse output signal following a first edge of the Nth edge of the input clock signal, and
a control input to receive a divisor input signal representing the adjustable integer number N K ;

an output circuit including a first clock output to provide a first output clock signal at a first output frequency having first and second edges, the output circuit providing the first edge of the first output clock signal between the first edge of the first pulse output signal and the first edge of the second pulse output signal;
a delta-sigma modulator (DSM), including a clock input to receive the second pulse output signal, a second input to receive a first predetermined value, and an output to provide a DSM output value; and
a phase accumulator circuit, including an input to receive a step input value representing a sum of the DSM output value and a second predetermined value, a first output coupled to provide the divisor input signal to the control input of the dynamic divider circuit, and a second output to provide a phase adjustment value to the output circuit to cause the output circuit to control a position of the first edge of the first output clock signal between the first edges of the first and second pulse output signals.

2. The FFD circuit of claim 1 , wherein the output circuit comprises:
a code mapping circuit to provide first and second multi-bit output values according to the phase adjustment value;
a phase interpolator circuit coupled to the dynamic divider circuit to receive the first and second pulse output signals, the phase interpolator circuit including an output to provide the first output clock signal, the phase interpolator circuit operative to control the position of the first edge of the first output clock signal between the first edges of the first and second pulse output signals according to a digital code provided by the code mapping circuit.

3. The FFD circuit of claim 2 , wherein the phase interpolator circuit has a fixed delay, and wherein a rising edge of the first output clock signal is adjustable and is not located between rising edges of the first and second pulse output signals.

4. The FFD circuit of claim 2 , wherein the phase interpolator circuit operates as a digital-to-time convertor according to only the first pulse output signal to generate the rising edge of the first output clock signal with an adjustable time delay according to the digital code from the code mapping circuit.

5. The FFD circuit of claim 2 , wherein the output circuit includes an integer divider circuit to receive an output signal from the phase interpolator circuit, the integer divider circuit including a second output to provide a second output clock signal at a second output frequency less than the first output frequency.

6. The FFD circuit of claim 2 ,
wherein the phase accumulator circuit includes a step accumulator circuit, the step accumulator circuit including:
a clock input to receive the second pulse output signal,
an input to receive the step input value,
a first step accumulator output to provide a carry forward value, and
a second step accumulator output to provide the phase adjustment value to the output circuit; and

wherein the first output of the phase accumulator circuit provides the divisor input signal to the control input of the dynamic divider circuit according to a sum of the carry forward value from the first step accumulator output and a third predetermined value.

7. The FFD circuit of claim 6 , wherein the first predetermined value, the second predetermined value, and the third predetermined value are configurable.

8. The FFD circuit of claim 1 , wherein the dynamic divider circuit operates as an edge counter to count only rising edges of the input clock signal, or to count only falling edges of the input clock signal, or to count all the rising and falling edges of the input clock signal.

9. The FFD circuit of claim 1 , wherein the first predetermined value and the second predetermined value are configurable.

10. The FFD circuit of claim 1 , wherein the first edge of the first pulse output signal is a rising edge and the second edge of the first pulse output signal is a falling edge, and wherein the first edge of the second pulse output signal is a rising edge and the second edge of the second pulse output signal is a falling edge.

11. A frequency divider system, comprising:
a phase locked loop circuit with an output to provide an input clock signal;
a plurality of fractional frequency divider (FFD) circuits, the individual FFD circuits including:
a dynamic divider circuit to count clock edges of the input clock signal having an input frequency and to provide phase shifted first and second pulse output signals in response to counting of an adjustable integer number N K cycles of the input clock signal, the dynamic divider circuit including:
a first output to provide the first pulse output signal including a first edge and a second edge, the first edge of the first pulse output signal following an Nth edge in a sequence of N K consecutive edges of the input clock signal,
a second output to provide the second pulse output signal including a first edge and a second edge, the first edge of the second pulse output signal following a first edge of the Nth edge of the input clock signal, and
a control input to receive a divisor input signal representing the adjustable integer number N K ,

an output circuit including a first clock output to provide a first output clock signal at a first output frequency having first and second edges, the output circuit providing the first edge of the first output clock signal between the first edge of the first pulse output signal and the first edge of the second pulse output signal,
a delta-sigma modulator (DSM), including a clock input to receive the second pulse output signal, a second input to receive a first predetermined value, and an output to provide a DSM output value, and
a phase accumulator circuit, including an input to receive a step input value representing a sum of the DSM output value and a second predetermined value, a first output coupled to provide the divisor input signal to the control input of the dynamic divider circuit, and a second output to provide a phase adjustment value to the output circuit to cause the output circuit to control a position of the first edge of the first output clock signal between the first edges of the first and second pulse output signals.

12. The frequency divider system of claim 11 , wherein the output circuit comprises:
a code mapping circuit to provide first and second multi-bit output values according to the phase adjustment value; and
a phase interpolator circuit coupled to the dynamic divider circuit to receive the first and second pulse output signals, the phase interpolator circuit including an output to provide the first output clock signal, the phase interpolator circuit operative to control the position

Assignees

• Texas Instruments Inc

Inventors

• Hoshyar Reza
• Zhou Wenting
• Kiaei Ali
• Haroun Baher
• Bahai Ahmad

Classifications

• H03L7/197

  a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division {(H03L7/1806 takes precedence)} · CPC title

• H03L7/16 Primary

  Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop · CPC title

• H03L7/1806

  the frequency divider comprising a phase accumulator generating the frequency divided signal · CPC title

• H03L7/1976 Primary

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title