Superconducting devices with enforced directionality

Patent metadata

Field	Value
Publication number	US-10153772-B2
Application number	US-201715425989-A
Country	US
Kind code	B2
Filing date	Feb 6, 2017
Priority date	Feb 6, 2017
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

Superconducting devices with enforced directionality and related methods are provided. In one example, a device including a first Josephson junction transmission line (JTL) for propagating a first set of quantum signals in a first direction and a second JTL for propagating a second set of quantum signals in the first direction is provided. The device may include a logic gate having a first input terminal for receiving the first set of quantum signals via the first JTL, and a second input terminal. The device may include a unidirectional buffer having a first input terminal for receiving the second set of quantum signals via the second JTL and an output terminal for coupling the second set of quantum signals to the second input terminal of the logic gate, where the unidirectional buffer may be configured to propagate quantum signals in only the first direction.

First claim

The invention claimed is:

1. A device comprising:
a first Josephson junction transmission line (JTL) for propagating a first set of quantum signals in a first direction;
a second Josephson junction transmission line (JTL) for propagating a second set of quantum signals in the first direction;
a logic gate comprising a plurality of Josephson junctions, wherein the logic gate having a first input terminal for receiving the first set of quantum signals via the first JTL, and a second input terminal; and
at least one unidirectional buffer having a first input terminal for receiving the second set of quantum signals via the second JTL and an output terminal for coupling the second set of quantum signals to the second input terminal of the at least one logic gate, wherein the unidirectional buffer is configured to propagate quantum signals in only the first direction.

2. The device of claim 1 , wherein the unidirectional buffer comprising:
a first inductive element coupled between a first terminal and a second terminal;
a first Josephson junction coupled between the second terminal and a ground terminal;
a second inductive element coupled between the second terminal and a third terminal; and
a second Josephson junction coupled between the third terminal and the ground terminal, wherein the second inductive element is configured to form an inductive loop comprising the first Josephson junction, the second inductive element, and the second Josephson junction.

3. The device of claim 2 , wherein the inductive loop is configured to store a current in the inductive loop.

4. The device of claim 3 , wherein the unidirectional buffer is configured to receive power via a clock signal comprising a plurality of phases, and wherein the clock signal is configured to provide a bias current to at least the second Josephson junction.

5. The device of claim 4 , wherein the unidirectional buffer is configured to propagate a quantum signal in the first direction when a sum of the bias current and the current stored by the inductive loop is sufficient to trigger the second Josephson junction.

6. The device of claim 1 , wherein each of the first set of quantum signals and the second set of quantum signals comprises single-flux quantum (SFQ) pulses.

7. The device of claim 6 , wherein the SFQ pulses comprise positive SFQ pulses and negative SFQ pulses.

8. A device comprising:
a first Josephson junction transmission line (JTL) for propagating a first set of quantum signals in a first direction;
a second Josephson junction transmission line (JTL) for propagating a second set of quantum signals in the first direction;
a logic gate comprising a plurality of Josephson junctions, wherein the logic gate having a first input terminal for receiving the first set of quantum signals via the first JTL, and a second input terminal; and
at least one unidirectional buffer having a first input terminal for receiving the second set of quantum signals via the second JTL and an output terminal for coupling the second set of quantum signals to the second input terminal of the at least one logic gate, wherein the unidirectional buffer is configured to propagate quantum signals in only the first direction, wherein the at least one unidirectional buffer comprising:
a first inductive element coupled between a first terminal and a second terminal;
a first Josephson junction coupled between the second terminal and a ground terminal;
a second inductive element coupled between the second terminal and a third terminal; and
a second Josephson junction coupled between the third terminal and the ground terminal, wherein the second inductive element is configured to form an inductive loop comprising the first Josephson junction, the second inductive element, and the second Josephson junction, wherein the first Josephson junction has a corresponding first critical current value and the second Josephson junction has a corresponding second critical current value, and wherein the first critical current value is approximately 1.1 to 1.4 times the second critical current value.

9. The device of claim 8 , wherein the inductive loop is configured to store a current in the inductive loop.

10. The device of claim 8 , wherein the unidirectional buffer is configured to receive power via a clock signal comprising a plurality of phases, and wherein the clock signal is configured to provide a bias current to at least the second Josephson junction.

11. The device of claim 10 , wherein the unidirectional buffer is configured to propagate a quantum signal in the first direction when a sum of the bias current and the current stored by the inductive loop is sufficient to trigger the second Josephson junction.

12. The device of claim 8 , wherein each of the first set of quantum signals and the second set of quantum signals comprises single-flux quantum (SFQ) pulses.

13. The device of claim 12 , wherein the SFQ pulses comprise positive SFQ pulses and negative SFQ pulses.

14. A unidirectional buffer comprising:
an input terminal for receiving quantum signals via a Josephson transmission line (JTL) configured to propagate signals in a first direction, wherein the unidirectional buffer is configured to propagate quantum signals in only the first direction and not in a second direction opposite to the first direction;
a first inductive element coupled between the input terminal and a second terminal;
a first Josephson junction coupled between the second terminal and a ground terminal
a second inductive element coupled between the second terminal and a third terminal; and
a second Josephson junction coupled between the third terminal and the ground terminal, wherein the second inductive element is configured to form an inductive loop comprising the first Josephson junction, the second inductive element, and the second Josephson junction, wherein the inductive loop is configured to store a current in the inductive loop, and wherein the unidirectional buffer is further configured to receive power via a clock signal comprising a plurality of phases, and wherein the clock signal is configured to provide a bias current to at least the second Josephson junction.

15. The unidirectional buffer of claim 14 , wherein the unidirectional buffer is further configured to propagate a quantum signal in the first direction when a sum of the bias current and the current stored by the inductive loop is sufficient to trigger the second Josephson junction.

16. The unidirectional buffer of claim 14 , wherein the quantum signals comprise single-flux quantum (SFQ) pulses.

17. The unidirectional buffer of claim 16 , wherein the SFQ pulses comprise positive SFQ pulses and negative SFQ pulses.

18. The unidirectional buffer of claim 14 , wherein the first Josephson junction has a corresponding first critical current value and the second Josephson junction has a corresponding second critical current value, and wherein the first critical current value is approximately 1.1 to 1.4 times the second critical current value.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Braun Alexander L

Classifications

• H03K19/195 Primary

  using superconductive devices · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• G11C19/32

  using super-conductive elements · CPC title

• G06F5/00

  Methods or arrangements for data conversion without changing the order or content of the data handled · CPC title

• H01L39/025

  Electricity · mapped topic