Method for controlling a semiconductor component

Patent metadata

Field	Value
Publication number	US-10153762-B2
Application number	US-201213436380-A
Country	US
Kind code	B2
Filing date	Mar 30, 2012
Priority date	Mar 30, 2012
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A transistor monolithically integrated in a semiconductor body includes a first sub-transistor and a second sub-transistor that both include a first and second load contacts and a control contact for controlling an electric current through a load path. The first load contact of the first sub-transistor is electrically connected to the first load contact of the second sub-transistor and the second load contact of the first sub-transistor is electrically connected to the second load contact of the second sub-transistor. A control circuit is configured to cause the first sub-transistor to switch from a first state to a second state at a first point of time and to cause the second sub-transistor to switch from the first state to the second state at a second point of time subsequent to the first point of time.

First claim

What is claimed is:

1. A method for controlling a semiconductor component that comprises a semiconductor body and a transistor monolithically integrated in the semiconductor body; wherein the transistor comprises a first sub-transistor and a second sub-transistor;
wherein the first sub-transistor comprises a first load contact, a second load contact, a first load path formed between the first load contact and the second load contact of the first sub-transistor, and a first control contact for controlling an electric current through the first load path;
wherein the second sub-transistor comprises a first load contact, a second load contact, a second load path formed between the first load contact and the second load contact of the second sub-transistor, and a second control contact for controlling an electric current through the second load path;
wherein the first load contact of the first sub-transistor is electrically connected to the first load contact of the second sub-transistor;
wherein the second load contact of the first sub-transistor is electrically connected to the second load contact of the second sub-transistor;
wherein the first sub-transistor has a first resistance in an ON-state and a higher second resistance in an OFF-state and the second sub-transistor has a third resistance in an ON-state and a higher fourth resistance in an OFF-state;
wherein the method comprises:
measuring a voltage drop over the first load path;
switching on the first sub-transistor to the ON-state at a first point of time; and
switching on the second sub-transistor to the ON-state at a second point of time subsequent to the first point of time in response to the measured voltage drop over the first load path falling below a first pre-defined value.

2. The method as claimed in claim 1 , wherein, after being switched on at the first point of time, the first sub-transistor is kept in its ON-state at least until the second point of time.

3. The method as claimed in claim 1 , further comprising switching the second sub-transistor to its OFF-state at a third point of time subsequent to the second point of time.

4. The method as claimed in claim 3 wherein:
the first sub-transistor is kept in its ON-state between the first point of time and the third point of time; and
the second sub-transistor is kept in its ON-state between the second point of time and the third point of time.

5. The method as claimed in claim 3 , further comprising switching the first sub-transistor to its OFF-state at a fourth point of time subsequent to the third point of time.

6. The method as claimed in claim 5 , wherein the second sub-transistor is kept in its OFF-state between the third point of time and the fourth point of time.

7. The method as claimed in claim 1 , wherein the first resistance is greater than the third resistance.

8. The method as claimed in claim 7 , wherein the first resistance is at least two times greater than the third resistance.

9. The method as claimed in claim 1 , further comprising controlling the first sub-transistor via the first control contact and the second sub-transistor via the second control contact, wherein the controlling is performed by a control circuit.

10. The method as claimed in claim 9 , wherein the control circuit is configured to provide control signals for controlling the first sub-transistor via the first control contact and the second sub-transistor via the second control contact.

11. The method as claimed in claim 9 , wherein the control circuit comprises a bidirectional switch that is coupled between the first control contact and the second control contact.

12. The method as claimed in claim 11 , wherein the bidirectional switch comprises a transfer gate.

13. The method as claimed in claim 1 , wherein the transistor is a DMOS transistor.

14. The method as claimed in claim 1 , comprising:
providing an inductive load that has a first contact and a second contact;
connecting the first contact to both the second load contact of the first sub-transistor and the second load contact of the second sub-transistor;
connecting both the first load contact of the first sub-transistor and the first load contact of the second sub-transistor to a first supply potential; and
connecting both second contact of the inductive load to a second supply potential that is different from the first supply potential.

15. The method as claimed in claim 1 , wherein the second sub-transistor is further switched to its ON-state at the second point of time if
an electric current through the first load path exceeds a second pre-defined value.

16. The method as claimed in claim 1 , wherein the second sub-transistor is switched to its ON-state at the second point of time if the absolute value of a voltage between the first control contact and the second load contact of the first sub-transistor exceeds a pre-defined value.

17. The method as claimed in claim 16 , wherein the first sub-transistor comprises a temperature compensation point and wherein the pre-defined value is greater than a value at which the first sub-transistor is operated above its temperature compensation point.

18. A method for operating a semiconductor component that comprises a semiconductor body and a transistor monolithically integrated in the semiconductor body, the transistor comprising a first sub-transistor having an ON-state and an OFF-state and a second sub-transistor having an ON-state and an OFF-state, the method comprising:
causing the first sub-transistor to be in its ON-state and the second sub-transistor to be in its ON-state, wherein the first sub-transistor comprises a first load contact, a second load contact, a first load path formed between the first load contact and the second load contact of the first sub-transistor, and a first control contact for controlling an electric current through the first load path and wherein the second sub-transistor comprises a first load contact, a second load contact, a second load path formed between the first load contact and the second load contact of the second sub-transistor, and a second control contact for controlling an electric current through the second load path, the first load contact of the first sub-transistor being electrically connected to the first load contact of the second sub-transistor and the second load contact of the first sub-transistor being electrically connected to the second load contact of the second sub-transistor;
measuring a voltage drop over the first load path;
switching the second sub-transistor to its OFF-state at a first point of time in response to the measured voltage drop over the first load path exceeding a first pre-defined value; and
switching the first sub-transistor to its OFF-state at a second point of time subsequent to the first point of time.

19. The method as claimed in claim 18 , wherein the second sub-transistor is further switched to its OFF-state at the first point of time if
an electric current through the first load path falls below a second pre-defined value.

20. The method as claimed in claim 18 , wherein the second sub-transistor is switched to its OFF-state at the first point of time if the absolute value of a voltage between the first control contact and the second load contact of the first sub-transistor falls below a pre-defined value.

21. The method as claimed in claim 20 , wherein the first sub-transistor comprises a temperature compensation point and wherein the pre-defined value is greater than a value at which the f

Assignees

• Ladurner Markus
• Illing Robert
• Infineon Technologies Ag

Inventors

• Ladurner Markus
• Illing Robert

Classifications

• H03K17/167

  using parallel switching arrangements · CPC title

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title