Three input comparator

Patent metadata

Field	Value
Publication number	US-10153757-B2
Application number	US-201615060539-A
Country	US
Kind code	B2
Filing date	Mar 3, 2016
Priority date	Mar 6, 2015
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A three input voltage comparator provides termination of a pulse width modulation (PWM) output in a switched mode power supply. Shutdown of the PWM signal occurs when a sense current from the switching transistors exceeds either or both of the limit and error current references. The three input voltage comparator replaces the generally used two input voltage comparator and also eliminates the necessity of having to provide a voltage clamping circuit on the output of the voltage error amplifier in the switched mode power supply. The three input voltage comparator may also comprise selectable polarity control for more versatile integration of it into a switched mode power supply design.

First claim

The invention claimed is:

1. A three input voltage comparator, comprising:
a first input;
a second input;
a third input; and
an output having either at a first or second logic level, wherein when voltages on:
the first input is less than the second and third inputs the output is at the first logic level,
the first input is greater than the second and less than the third input the output is at the second logic level,
the first input is greater than the second and third inputs the output is at the second logic level, and
the first input is less than the second and greater than the third input the output is at the second logic level.

2. The three input voltage comparator according to claim 1 , wherein the first logic level is a high logic level and the second logic level is a low logic level.

3. The three input voltage comparator according to claim 1 , wherein the first logic level is a low logic level and the second logic level is a high logic level.

4. The three input voltage comparator according to claim 1 , wherein the first and third inputs are non-inverting inputs and the second input is an inverting input.

5. A three input voltage comparator having output polarity control, comprising:
a first voltage comparator having a first input, a second input and a first output;
a second voltage comparator having a third input and the second input in common with the first voltage comparator, and a second output;
a first exclusive OR gate having a first input coupled to the output of the first voltage comparator and a second input coupled to a first polarity selection signal;
a second exclusive OR gate having a first input coupled to the output of the second voltage comparator and a second input coupled to a second polarity selection signal;
an AND gate having a first input coupled to an output of the first exclusive OR gate and a second input coupled to an output of the second exclusive OR gate; and
a third exclusive OR gate having a first input coupled to the output of the AND gate, a second input coupled to a third polarity selection signal, and a third output,
wherein the first and third inputs are non-inverting inputs and the second input is an inverting input.

6. The three input voltage comparator according to claim 5 , wherein when a voltage on the second input is greater than voltages on the first and third inputs of the voltage comparators then the third output of the third exclusive OR gate is at a logic low when the first, second and third polarity selection signals are at the logic low.

7. The three input voltage comparator according to claim 5 , wherein when a voltage on the second input is greater than a voltage on the first input and less than a voltage on the third input of the voltage comparators then the third output of the third exclusive OR gate is at a logic low when the first, second and third polarity selection signals are at the logic low.

8. The three input voltage comparator according to claim 5 , wherein when a voltage on the second input is less than a voltage on the first input and greater than a voltage on the third input of the voltage comparators then the third output of the third exclusive OR gate is at a logic low when the first, second and third polarity selection signals are at the logic low.

9. The three input voltage comparator according to claim 5 , wherein when a voltage on the second input is less than voltages on the first and third inputs of the voltage comparators then the third output of the third exclusive OR gate is at a logic high when the first, second and third polarity selection signals are at a logic low.

10. The three input voltage comparator according to claim 5 , wherein when a voltage on the second input is greater than voltages on the first and third inputs of the voltage comparators then the third output of the third exclusive OR gate is at a logic high when the first polarity selection signal is at a logic low, and the second and third polarity selection signals are at the logic high.

11. The three input voltage comparator according to claim 5 , wherein when a voltage on the second input is greater than the voltage on the first input and less than the voltage on the third input of the voltage comparators then the third output of the third exclusive OR gate is at a logic high when the first polarity selection signal is at a logic low, and the second and third polarity selection signals are at the logic high.

12. The three input voltage comparator according to claim 5 , wherein when a voltage on the second input is less than the voltage on the first input and greater than the voltage on the third input of the voltage comparators then the third output of the third exclusive OR gate is at a logic low when the first polarity selection signal is at the logic low, and the second and third polarity selection signals are at a logic high.

13. The three input voltage comparator according to claim 5 , wherein when a voltage on the second input is less than the voltages on the first and third inputs of the voltage comparators then the third output of the third exclusive OR gate is at a logic high when the first polarity selection signal is at a logic low, and the second and third polarity selection signals are at the logic high.

14. The three input voltage comparator according to claim 5 , wherein when a voltage on the second input is greater than the voltages on the first and third inputs of the voltage comparators then the third output of the third exclusive OR gate is at a logic high when the first polarity selection signal is at the logic high, the second polarity selection signal is at a logic low, and the third polarity selection signal is at the logic high.

15. The three input voltage comparator according to claim 5 , wherein when a voltage on the second input is greater than the voltage on the first input and less than the third input of the voltage comparators then the third output of the third exclusive OR gate is at a logic low when the first polarity selection signal is at a logic high, the second polarity selection signal is at the logic low, and the third polarity selection signal is at the logic high.

16. The three input voltage comparator according to claim 5 , wherein when a voltage on the second input is less than the voltage on the first input and greater than the third input of the voltage comparators then the third output of the third exclusive OR gate is at a logic high when the first polarity selection signal is at the logic high, the second polarity selection signal is at a logic low, and the third polarity selection signal is at the logic high.

17. The three input voltage comparator according to claim 5 , wherein when a voltage on the second input is less than the voltages on the first and third inputs of the voltage comparators then the third output of the third exclusive OR gate is at a logic high when the first polarity selection signal is at the logic high, the second polarity selection signal is at a logic low, and the third polarity selection signal is at the logic high.

18. A microcontroller comprising a digital processor and a three input voltage comparator comprising:
a first voltage comparator having a first input, a second input and a first output;
a second voltage comparator having a third input and the second input in common with the first voltage comparator, and a second output;
a first exclusive OR gate having a first input coupled to the output of the first voltage comparator and a second input coupled to a first polarity selection signal;
a second exclusive OR gate havin

Assignees

• Microchip Tech Inc

Inventors

• Van Eeden Jacobus Albertus
• Yuenyongsgool Yong
• Curtis Keith

Classifications

• H03K5/2481 Primary

  with at least one differential stage · CPC title

• H03K5/24 Primary

  the characteristic being amplitude · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title