Eliminating systematic imbalances and reducing circuit parameter variations in high gain amplifiers
US-2015381118-A1 · Dec 31, 2015 · US
US10153743B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10153743-B2 |
| Application number | US-201715719043-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 28, 2017 |
| Priority date | Sep 22, 2016 |
| Publication date | Dec 11, 2018 |
| Grant date | Dec 11, 2018 |
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The present invention is directed to electrical circuits and techniques thereof. More specifically, an embodiment of the present invention provides a variable gain amplifier that includes a first transistor and a second transistor whose gate terminals are coupled to a first input terminal. A first drain terminal of the first transistor and a first source terminal of the second transistor is coupled to a voltage gain control switch. There are other embodiments as well.
Opening claim text (preview).
What is claimed is: 1. A variable gain amplifier (VGA) device comprising: a first input terminal and a second input terminal; a first output terminal and a second output terminal; a first NMOS switch comprising a first source terminal, a first drain terminal, and a first gate terminal, the first gate terminal being coupled to the first input terminal, the first drain terminal being coupled to the first output terminal; a second NMOS switch comprising a second source terminal, a second drain terminal, and a second gate terminal, the second drain terminal being coupled to the first source terminal, the second source terminal being coupled to a ground terminal, the second gate terminal being coupled to the first input terminal; a third NMOS switch coupled to the second output terminal and the second input terminal; a fourth NMOS switch coupled to the ground terminal and the second input terminal; a voltage control module comprising a control terminal, the voltage control module being coupled to the first source terminal and the second drain terminal, wherein the device further comprises a common mode resistor coupled to the first output terminal. 2. The device of claim 1 wherein the voltage control module is further coupled to the third NMOS switch and the fourth NMOS switch. 3. The device of claim 1 further comprising a load resistor coupled to the first drain terminal. 4. The device of claim 1 wherein the voltage control module comprises an NMOS transistor, a gate terminal of the NMOS transistor being coupled to the control terminal. 5. The device of claim 1 wherein third NMOS switch comprises a third drain terminal, a third source terminal, and a third gate terminal, the third gate terminal being coupled to the second input terminal, the third source terminal being coupled to the voltage control module. 6. A variable gain amplifier (VGA) device comprising: a first input terminal and a second input terminal; a voltage source; a first PMOS switch comprising a first source terminal, a first drain terminal, and a first gate terminal, the first gate terminal being coupled to the first input terminal, the first source terminal being coupled to the voltage source; a second PMOS switch comprising a second source terminal, a second drain terminal, and a second gate terminal, the second source terminal being coupled to the first drain terminal, the second gate terminal being coupled to the first input terminal; a third PMOS switch comprising a third source terminal, a third drain terminal, and a third gate terminal, the third gate terminal being coupled to the second input terminal; a fourth PMOS switch comprising a fourth source terminal, a fourth drain terminal, and a fourth gate terminal, the fourth gate terminal being coupled to the second input terminal and the third PMOS switch; and a voltage control module comprising a control terminal, the voltage control module being coupled to the first drain terminal and the third drain terminal. 7. The device of claim 6 wherein the voltage control module comprises a PMOS transistor. 8. The device of claim 6 further comprising a first load resistor coupled to the second drain terminal. 9. The device of claim 8 wherein the first load resistor is coupled to a ground terminal. 10. The device of claim 9 further comprising a second load resistor coupled to the fourth PMOS switch. 11. The device of claim 6 wherein the VGA device is characterized by a first gain value and the voltage control module is characterized by a second gain value, the first gain value being substantially equal to the second gain value. 12. The device of claim 6 wherein the second drain terminal is coupled to a first output terminal. 13. The device of claim 6 wherein the third source terminal of the third PMOS switch is coupled to the voltage source. 14. A variable gain amplifier (VGA) device comprising: a first input terminal and a second input terminal; a first PMOS switch comprising a first source terminal, a first drain terminal, and a first gate terminal, the first gate terminal being coupled to the first input terminal; a second PMOS switch comprising a second source terminal, a second drain terminal, and a second gate terminal, the second source terminal being coupled to the first drain terminal, the second gate terminal being coupled to the first input terminal; a third PMOS switch comprising a third drain terminal, a third source terminal, and a third gate terminal, the third gate terminal being coupled to the second input terminal; a fourth PMOS switch comprising a fourth drain terminal, a fourth source terminal, and a fourth gate terminal coupled to the second input terminal, the fourth source terminal being coupled to the third drain terminal; and a fifth PMOS switch comprising a fifth drain terminal, a fifth source terminal, and a fifth gate terminal coupled to a gain control signal, the fifth PMOS switch being coupled to and disposed between the first drain terminal and the third drain terminal. 15. The device of claim 14 wherein the fifth drain terminal is coupled to the first drain terminal. 16. The device of claim 15 wherein the fifth source terminal is coupled to the third drain terminal. 17. The device of claim 15 further comprising a load resistor coupled to the second drain terminal. 18. The device of claim 17 wherein the load resistor is coupled to a ground terminal. 19. The device of claim 15 further comprising a voltage source coupled to the third source terminal.
the bias at the input of the amplifying transistors being controlled · CPC title
the CSC comprising biasing means controlled by the input signal · CPC title
using field-effect transistors [FET] · CPC title
using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title
in emitter-coupled or cascode amplifiers (H03G1/0029 takes precedence) · CPC title
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