Apparatus and method of fast commutation for matrix converter-based rectifier

Patent metadata

Field	Value
Publication number	US-10153686-B2
Application number	US-201815975827-A
Country	US
Kind code	B2
Filing date	May 10, 2018
Priority date	Mar 25, 2015
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A method of commutation in a matrix rectifier from an active vector to a zero vector includes two steps. A method of commutation in a matrix rectifier from a zero vector to an active vector includes three steps.

First claim

What is claimed is:

1. A matrix rectifier comprising:
first, second, and third phases; and
uni-directional switches S ij , where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where uni-directional switches S 1j and S 2j are connected together to define first, second, third, fourth, fifth, and sixth bi-directional switches; wherein
first ends of the first, third, and fifth bidirectional switches are connected together to provide a positive-voltage node;
first ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negative-voltage node;
second ends of the first and fourth bidirectional switches are connected to the first phase;
second ends of the third and sixth bidirectional switches are connected to the second phase;
second ends of the fifth and second bidirectional switches are connected to the third phase;
a zero vector is defined by either uni-directional switches S 1m and S 1n switched on or uni-directional switches S 2m and S 2n switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other uni-directional switches S pq switched off, where p≠m and q≠n; and
an active vector is defined by either uni-directional switches S 1m and S 1n switched on or uni-directional switches S 2m and S 2n switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other uni-directional switches S pq switched off, where p≠m and q≠n;
Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6);
commutation from an active vector to a zero vector includes:
step (a):
for an active vector with uni-directional switches S 1m and S 1n switched on,
in Sectors I, III, V, turning on uni-directional switch S 1x , where x is chosen such that (m, x)=(1, 4), (3, 6), (5, 2); and
in Sectors II, IV, VI, turning on uni-directional switch S 1x , where x is chosen such that (x, n)=(1, 4), (3, 6), (5, 2); or

for an active vector with uni-directional switches S 2m and S 2n switched on,
in Sectors I, III, V, turning on uni-directional switch S 2y , where y is chosen such that (y, n)=(1, 4), (3, 6), (5, 2); and
in Sectors II, IV, VI, turning on uni-directional switch S 2y , where y is chosen such that (m, y)=(1, 4), (3, 6), (5, 2); and

step (b):
for the active vector with uni-directional switches S 1m and S 1n initially switched on,
in Sectors I, III, V, turning off uni-directional switch S 1n ; and
in Sectors II, IV, VI, turning off uni-directional switch S 1m ; or

for the active vector with uni-directional switches S 2m and S 2n initially switched on,
in Sectors I, III, V, turning off uni-directional switch S 2m ;
in Sectors II, IV, VI, turning off uni-directional switch S 2n .

2. The matrix rectifier of claim 1 , wherein the commutation includes measuring input voltage and not measuring output current or output voltage.

3. The matrix rectifier of claim 1 , wherein the first, second, third, fourth, fifth, and sixth bi-directional switches are modulated based on space vector modulation.

4. The matrix rectifier of claim 3 , wherein gate signals s ij applied to the uni-directional switches S ij are generated by:
determining a space-vector-modulation sector; and
generating:
a carrier signal;
first, second, and third comparison signals based on dwell times of corresponding zero vector and two active vectors of the space-vector-modulation sector;
modulation signals s j corresponding to the first, second, third, fourth, fifth, and sixth bi-directional switches based on the comparison of the carrier signal and the first, second, and third comparison signals, where j=1, 2, 3, 4, 5, 6; and
a first converter select signal SelectCon 1 and a second converter select signal SelectCon 2 based on if a positive or a negative voltage is outputted; wherein

the gate signals s ij are generated based on:
s 1j =s j ×SelectCon1( j= 1,3,5,4,6,2)

s 2j =s j ×SelectCon2( j= 1,3,5,4,6,2).

5. A matrix rectifier comprising:
first, second, and third phases; and
uni-directional switches S ij , where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where uni-directional switches S ij and S 2j are connected together to define first, second, third, fourth, fifth, and sixth bi-directional switches; wherein
first ends of the first, third, and fifth bidirectional switches are connected together to provide a positive-voltage node;
first ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negative-voltage node;
second ends of the first and fourth bidirectional switches are connected to the first phase;
second ends of the third and sixth bidirectional switches are connected to the second phase;
second ends of the fifth and second bidirectional switches are connected to the third phase;
a zero vector is defined by either uni-directional switches S 1m and S 1n switched on or uni-directional switches S 2m and S 2n switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other uni-directional switches S pq switched off, where p≠m and q≠n;
an active vector is defined by either uni-directional switches S 1m and S 1n switched on or uni-directional switches S 2m and S 2n switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other uni-directional switches S pq switched off, where p≠m and q≠n; and
Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6);
commutation from a zero vector to an active vector includes:
step (a):
for a zero vector with uni-directional switches S 1m and S 1n switched on,
in Sectors I, III, V, turning on uni-directional switch S 1x , where x=1, 3, 5 and x is chosen such that a negative voltage is provided at the positive-voltage node; and
in Sectors II, IV, VI, turning on uni-directional switch S 1x , where x=2, 4, 6 and x is chosen such that a positive voltage is provided at the negative-voltage node; or

for a zero vector with uni-directional switches S 2m and S 2n switched on,
in Sectors I, III, V, turning on uni-directional switch S 2y , where y=2, 4, 6 and y is chosen such that a positive voltage is provided at the negative-voltage node; and
in Sectors II, IV, VI, turning on uni-directional switch S 2y , where y=1, 3, 5 and y is chosen such that a negative voltage is provided at the positive-voltage node;

step (b):
for the zero vector with uni-directional switches S 1m and S 1n initially switched on,
in Sectors I, III, V, turning off uni-directional switch S 1m ; and
in Sectors II, IV, VI, turning off uni-directional switch S 1n ; or

for the zero vector with uni-directional switches S 2m and S 2n initially switched on,
in Sectors I, III, V, turning off uni-directional switch S 2n ; and
in Sectors II, IV, VI, turning off uni-directional switch S 2m ; and

step (c):
for the zero vector with uni-directional switches S 1m and S 1n initially switched on,
in Sectors I, III, V, turning off uni-directional switches S 1x and S 1n and turning on uni-directional switches S 2x and S 2n ; and
in Sectors II, IV, VI, turning off uni-directional switches S 1x and S 1m and turning on uni-directional switches S 2x and S 2m ; or

for the zero vector with uni-directional switches S 2m and S 2n initially switched on,
in Sectors I, III, V, turning off uni-directional switches S 2m and S 2y and turning on uni-directional switches S 1m and S 1y ; and
in Sectors II, IV, VI, turning off uni-directional switches S 2n and S 2y and turning on uni-directional switches S 1n and S 1y .

6. The matrix rectifier of claim 5 , wherein the commutation includes measuring input voltage and not measuring output c

Assignees

• Murata Manufacturing Co

Inventors

• Zhao Tao
• Xu Dewei
• Afsharian Jahangir
• Gong Bing
• Yang Zhihua

Classifications

• H02M1/38 Primary

  Means for preventing simultaneous conduction of switches · CPC title

• H02M7/1552

  in a biphase or polyphase arrangement (voltage multipliers H02M7/19) · CPC title

• H02M1/088 Primary

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title

• H02M7/219 Primary

  in a bridge configuration · CPC title

• H02M7/162

  in a bridge configuration · CPC title