Transistor having high electron mobility and method of its manufacture

Patent metadata

Field	Value
Publication number	US-10153363-B2
Application number	US-201615738464-A
Country	US
Kind code	B2
Filing date	Apr 27, 2016
Priority date	Jun 29, 2015
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A method for manufacturing a transistor having high electron mobility, encompassing a substrate having a heterostructure, in particular an AlGaN/GaN heterostructure, having the steps of: generation of a gate electrode by patterning a semiconductor layer that is applied onto the heterostructure, the semiconductor layer encompassing, in particular, polysilicon; application of a passivating layer onto the semiconductor layer; formation of drain regions and source regions by generation of first vertical openings that extend at least into the heterostructure; generation of ohmic contacts in the drain regions and in the source regions by partly filling the first vertical openings with a first metal at least to the height of the passivating layer; and application of a second metal layer onto the ohmic contacts, the second metal layer projecting beyond the passivating layer.

First claim

What is claimed is:

1. A method for manufacturing a transistor having high electron mobility, encompassing a substrate having an AlGaN/GaN heterostructure, comprising:
generating a gate electrode by patterning a semiconductor layer that is applied directly or indirectly onto the heterostructure, the semiconductor layer encompassing polysilicon;
applying a passivating layer onto the semiconductor layer;
forming drain and source regions by generating first vertical openings that extend at least into the heterostructure;
generating ohmic contacts in the drain regions and in the source regions by partly filling the first vertical openings with a first metal from in the heterostructure into the passivating layer, forming respective top surfaces in the passivating layer; and
applying respective second metal layers onto the top surfaces of the ohmic contacts in the passivating layer, the second metal layer projecting upward, through and beyond a top of the passivating layer.

2. The method as recited in claim 1 , further comprising:
applying an insulating layer onto the heterostructure, the insulating layer being disposed between the heterostructure and the passivating layer, the insulating layer functioning as a gate insulator.

3. The method as recited in claim 1 , further comprising:
generating a second vertical opening in the region of the gate electrodes, which extends as far as a surface of the semiconductor layer; and
applying a third metal layer onto the gate electrode.

4. The method as recited in claim 1 , further comprising:
patterning a dielectric layer that is disposed on the heterostructure to pattern the gate electrode.

5. The method as recited in claim 1 , further comprising:
applying an insulating layer onto the heterostructure, the insulating layer being disposed between the heterostructure and the semiconductor layer, made of polysilicon, which functions as a gate electrode, the insulating layer functioning as a gate insulator.

6. A transistor having high electron mobility, the transistor comprising:
an AlGaN/GaN heterostructure;
a polysilicon gate electrode directly or indirectly on the heterostructure;
a passivating layer partially on at least a part of the semiconductor layer;
a drain region including:
a first metal as a first ohmic contact extending from in the heterostructure into the passivating layer, with a first top surface in the passivating layer; and
a second metal extending upward from the first top surface in the passivating layer through and beyond a top of the passivating layer; and

a source region including:
the first metal as a second ohmic contact extending from in the heterostructure into the passivating layer, with a second top surface in the passivating layer; and
the second metal extending upward from the second top surface in the passivating layer through and beyond the top of the passivating layer.

7. The transistor as recited in claim 6 , wherein the gate electrode is T-shaped.

8. The transistor as recited in claim 6 , wherein the gate electrode is metal free.

9. The transistor as recited in claim 6 , further comprising a dielectric layer below a first part of the gate electrode, wherein a second part of the gate electrode extends downwards into the dielectric layer, the second part being positioned asymmetrically relative to the first part of the gate electrode, closer to one of the drain and source regions than the other of the drain and source regions.

10. The transistor as recited in claim 9 , further comprising an insulating layer separating a bottom of the second part of the gate electrode from the heterostructure.

11. The transistor as recited in claim 10 , wherein the insulating layer extends from over a top surface of the dielectric layer downward into the dielectric layer, reaching the heterostructure.

12. The transistor as recited in claim 6 , further comprising an insulating layer on the heterostructure layer, separating between the heterostructure layer and (a) the gate electrode, which is arranged on the insulating layer, and (b) a part of the passivating layer arranged on the insulating layer.

13. The transistor as recited in claim 12 , wherein a part of the gate electrode is arranged on a top surface of the passivating layer.

Assignees

• Bosch Gmbh Robert

Inventors

• Grieb Michael
• Jauss Simon
• Schwaiger Stephan

Classifications

• H01L29/66462

  Electricity · mapped topic

• H01L29/42376

  Electricity · mapped topic

• H01L29/4916

  Electricity · mapped topic

• H01L29/7787 Primary

  Electricity · mapped topic

• H01L29/205

  Electricity · mapped topic