Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10153358-B2
Application number	US-201615390754-A
Country	US
Kind code	B2
Filing date	Dec 27, 2016
Priority date	Feb 17, 2016
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A semiconductor device includes a fin structure which vertically protrudes from a substrate and extends in a first direction parallel to a top surface of the substrate. The fin structure includes a lower pattern and an active pattern vertically protruding from a top surface of the lower pattern. The top surface of the lower pattern includes a flat portion substantially parallel to the top surface of the substrate. The lower pattern includes a first sidewall extending in the first direction and a second sidewall extending in a second direction crossing the first direction. The first sidewall is inclined relative to the top surface of the substrate at a first angle greater than a second angle corresponding to the second sidewall that is inclined relative to the top surface of the substrate.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a fin structure vertically protruding from a substrate and extending in a first direction parallel to a top surface of the substrate; and
a first device isolation pattern on the substrate, wherein the fin structure includes a lower pattern and an active pattern vertically protruding from a top surface of the lower pattern, wherein the top surface of the lower pattern includes a flat portion parallel to the top surface of the substrate, wherein the lower pattern includes a first sidewall extending in the first direction and a second sidewall extending in a second direction crossing the first direction, the first sidewall inclined relative to the top surface of the substrate at a first angle greater than a second angle corresponding to the second sidewall that is inclined relative to the top surface of the substrate, and wherein the first device isolation pattern covers the flat portion and at least one sidewall of a lower portion of the active pattern and exposes an upper portion of the active pattern.

2. The semiconductor device as claimed in claim 1 , wherein the active pattern includes a third sidewall extending in the first direction and inclined relative to the top surface of the substrate at a third angle different from the first and second angles.

3. The semiconductor device as claimed in claim 1 , wherein:
the fin structure includes a length in the first direction and a width in the second direction, and
a ratio of a maximum length to a maximum width is about 3.5 to about 5.

4. The semiconductor device as claimed in claim 1 , further comprising
a second device isolation pattern on the substrate adjacent to the first device isolation pattern, wherein the second device isolation pattern covers the first sidewall of the lower pattern, and wherein a top surface of the first device isolation pattern is coplanar with a top surface of the second device isolation pattern.

5. The semiconductor device as claimed in claim 1 , further comprising
a contact plug on the substrate and electrically connected to the active pattern,
wherein the contact plug is to apply a voltage to the substrate through the fin structure.

6. The semiconductor device as claimed in claim 1 , further comprising:
a gate electrode running across the active pattern and extending in the second direction on the substrate; and
a source/drain pattern adjacent to at least one side of the gate electrode and on the active pattern.

7. A semiconductor device, comprising:
a fin structure vertically protruding from a substrate and extending in a first direction parallel to a top surface of the substrate, the fin structure including a lower pattern and an active pattern vertically protruding from a top surface of the lower pattern; and
a device isolation layer surrounding the lower pattern and a lower portion of the active pattern and exposing an upper portion of the active pattern, wherein the lower pattern includes a first sidewall extending in the first direction, the first sidewall inclined relative to the top surface of the substrate at a first angle, and wherein the lower portion of the active pattern includes a second sidewall extending in the first direction and inclined relative to the top surface of the substrate at a second angle different from the first angle.

8. The semiconductor device as claimed in claim 7 , wherein the lower pattern includes a third sidewall extending in a second direction crossing the first direction, the third sidewall inclined relative to the top surface of the substrate at a third angle smaller than the first angle.

9. The semiconductor device as claimed in claim 7 , wherein:
the fin structure includes a length in the first direction and a width in the second direction, and
a ratio of a maximum length to a maximum width is about 3.5 to about 5.

10. The semiconductor device as claimed in claim 7 , further comprising
a contact plug on the substrate and electrically connected to the active pattern, wherein the contact plug is to apply a voltage to the substrate through the fin structure.

11. The semiconductor device as claimed in claim 7 , further comprising:
a gate electrode running across the active pattern and extending in the second direction on the substrate; and
a source/drain pattern adjacent to at least one side of the gate electrode and on the active pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• MIN Kyungseok
• Nam Seongjin
• Sung Sughyun
• Oh Youngmook
• Gwon Migyeong
• KIM Hyungdong
• Park Inwon
• Lee Hyunggoo

Classifications

• H10P72/722

  Details of electrostatic chucks · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P50/73

  using masks for insulating materials · CPC title