Semiconductor device and a display device including the same

Patent metadata

Field	Value
Publication number	US-10153336-B2
Application number	US-201715583244-A
Country	US
Kind code	B2
Filing date	May 1, 2017
Priority date	May 2, 2016
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A semiconductor device including a semiconductor layer, a first electrode, and a second electrode. The semiconductor layer includes a first source region, a first drain region, a second source region, and a second drain region connected to a channel region. The first gate electrode is disposed below the semiconductor layer. The first gate electrode is insulated from the semiconductor layer. The first gate electrode at least partially overlaps the shared channel region. The second gate electrode is disposed above the semiconductor layer. The second gate electrode is insulated by a second gate insulating layer. The second gate electrode at least partially overlaps the channel region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor layer, the semiconductor layer comprising a first source region, a first drain region, a second source region, and a second drain region connected to a channel region;
a first gate electrode disposed below the semiconductor layer, the first gate electrode insulated from the semiconductor layer by a first gate insulating layer, and at least partially overlapping the channel region; and
a second gate electrode disposed above the semiconductor layer, the second gate electrode insulated by a second gate insulating layer, and at least partially overlapping the channel region.

2. The semiconductor device of claim 1 , wherein a first thin film transistor comprises the channel region, the first source region, the first drain region, and the first gate electrode, and
a second thin film transistor comprises the channel region, the second source region, the second drain region, and the second gate electrode.

3. The semiconductor device of claim 1 , wherein a thickness of the first gate insulating layer is different than a thickness of the second gate insulating layer.

4. The semiconductor device of claim 1 , further comprising;
an interlayer insulating layer disposed above the second gate electrode; and
a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode disposed above the interlayer insulating layer, wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are respectively connected to the first source region, the first drain region, the second source region, and the second drain region via contact holes.

5. The semiconductor device of claim l, further comprising:
a capacitor comprising a first electrode and a second electrode,
wherein the first electrode is connected to the second gate electrode,
wherein the second electrode is disposed above the first electrode and insulated from the first electrode, and
wherein the second gate electrode and the first electrode form a single structure in a same layer.

6. The semiconductor device of claim 5 , wherein the capacitor comprises a third gate insulating layer, the third gate insulating layer disposed between the first electrode and the second electrode.

7. The semiconductor device of claim 1 , wherein the first source region, the first drain region, the second source region, and the second drain region are spaced apart from each other.

8. The semiconductor device of claim 1 , wherein the first source region and the second source region form a single region, and the first drain region is spaced apart from the second drain region.

9. The semiconductor device of claim 1 , wherein the first source region is spaced apart from the second source region, and the first drain region and the second drain region form a single region.

10. A display device, comprising:
the semiconductor device of claim 1 ;
a planarization layer covering the semiconductor device;
a pixel electrode disposed above the planarization layer and connected to one of the first source region, the first drain region, the second source region, or the second drain region;
an opposite electrode facing the pixel electrode; and
an intermediate layer disposed between the pixel electrode and the opposite electrode.

11. The display device of claim 10 , wherein a first thin film transistor comprises the channel region, the first source region, the first drain region, and the first gate electrode, and
a second thin film transistor comprises the channel region, the second source region, the second drain region, and the second gate electrode.

12. The display device of claim 10 , further comprising:
a gate line configured to transfer a gate signal, a data line configured to transfer a data signal, and a driving voltage line configured to transfer a driving voltage, wherein the gate line is connected to the first gate electrode, the data line is connected to the first source region, the driving voltage line is connected to the second source region, and the pixel electrode is connected to the second drain region.

13. The display device of claim 12 , wherein a thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer.

14. The display device of claim 10 , further comprising:
a capacitor comprising a first electrode connected to the second gate electrode and a second electrode disposed above the first electrode and insulated from the first electrode,
wherein the second gate electrode and the first electrode form a single structure in a same layer.

15. The display device of claim 14 , wherein the capacitor comprises a third gate insulating layer disposed between the first electrode and the second electrode.

16. The display device of claim 10 , further comprising an auxiliary capacitor, wherein the auxiliary capacitor does not overlap the semiconductor device.

17. The display device of claim 10 , further comprising a pixel-defining layer, wherein the pixel-defining layer exposes a portion of the pixel electrode, covers a surface of the pixel electrode, and defines a pixel.

18. The display device of claim 10 , wherein the intermediate layer comprises an organic emission layer.

19. A semiconductor device, comprising:
a substrate;
a semiconductor layer including a channel region disposed above the substrate;
a first gate electrode, the first gate electrode at least partially overlapping the channel region;
a second gate electrode disposed above the semiconductor layer, the second gate electrode at least partially overlapping the channel region;
wherein the semiconductor layer overlaps the first gate electrode when viewed from above the semiconductor layer towards the substrate.

20. The semiconductor device of claim 19 , wherein the semiconductor layer further comprises a first source region, a first drain region, a second source region, and a second drain region.

21. The semiconductor device of claim 20 , wherein a first thin film transistor comprises the channel region, the first source region, the first drain region, and the first gate electrode, and
a second thin film transistor comprises the channel region, the second source region, the second drain region, and the second gate electrode.

22. The semiconductor device of claim 19 , wherein the first gate electrode is insulated by a first gate insulating layer, and the second gate electrode is insulated by a second gate insulating layer.

23. The semiconductor device of claim 22 , wherein a thickness of the first gate insulating layer is different than a thickness of the second gate insulating layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Waljun
• Kim Yeonhong
• Kim Junghyun
• Kim Taejin
• Ahn Kiwan
• Jang Yongjae

Classifications

• H01L27/3246

  Electricity · mapped topic

• H01L27/124

  Electricity · mapped topic

• H01L27/1255

  Electricity · mapped topic

• H01L27/1248

  Electricity · mapped topic

• H01L27/3276 Primary

  Electricity · mapped topic