Semiconductor device

Patent metadata

Field	Value
Publication number	US-10153266-B2
Application number	US-201615272439-A
Country	US
Kind code	B2
Filing date	Sep 22, 2016
Priority date	Sep 11, 2013
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

First claim

What is claimed is:

1. A semiconductor workpiece arrangement comprising:
a semiconductor wafer comprising a substrate region, a device region disposed over the substrate region, and one or more kerf regions;
a patterned metallization layer disposed over the substrate region at a back side of the semiconductor wafer, the back side of the semiconductor wafer being opposite to a front side of the semiconductor wafer; and
a plating layer disposed on the patterned metallization layer at least on a back side of the patterned metallization layer facing away from the semiconductor wafer, and
a stack arrangement disposed between the substrate region of the semiconductor wafer and the patterned metallization layer,
wherein the patterned metallization layer covers the back side of the semiconductor wafer except for the one or more kerf regions of the semiconductor wafer.

2. The semiconductor workpiece arrangement of claim 1 , wherein the stack arrangement comprises a sequence of aluminum (Al) and titanium (Ti).

3. The semiconductor workpiece arrangement of claim 2 , further comprising:
a seed layer disposed between the stack arrangement and the patterned metallization layer.

4. The semiconductor workpiece arrangement of claim 3 , wherein the seed layer is a copper seed layer.

5. The semiconductor workpiece arrangement of claim 1 , wherein the patterned metallization layer comprises at least one material selected from a group of materials, the group consisting of: copper, tin, nickel, gold, silver, palladium, zinc, iron, titanium, an alloy comprising at least one of the aforementioned materials.

6. The semiconductor workpiece arrangement of claim 1 , wherein the semiconductor wafer has a thickness so that a mechanical stability of the semiconductor wafer is insufficient to resist the at least one back end process without damage, and wherein the patterned metallization layer has a thickness so that a mechanical stability of the semiconductor wafer is increased to be sufficient to resist the at least one back end process without damage, wherein the thicknesses are measured in a direction parallel to the direction from the front side of the semiconductor wafer to the back side of the semiconductor wafer.

7. The semiconductor workpiece arrangement of claim 6 , wherein the thickness of the semiconductor wafer is less than or equal to about 50 μm.

8. The semiconductor workpiece arrangement of claim 6 , wherein the thickness of the patterned metallization layer is greater than or equal to about 10 μm.

9. The semiconductor workpiece arrangement of claim 1 , wherein the patterned metallization layer comprises a material that has a resistivity of less than or equal to about 1×10 −6 Ωm.

10. The semiconductor workpiece arrangement of claim 1 , wherein the semiconductor wafer comprises one or more through-silicon (TS) diodes.

11. The semiconductor workpiece arrangement of claim 1 , further comprising:
a carrier wafer disposed over the device region at the front side of the semiconductor wafer.

12. A semiconductor workpiece arrangement comprising:
a semiconductor wafer comprising a substrate region, a device region disposed over the substrate region, and one or more kerf regions;
a patterned metallization layer disposed over the substrate region at a back side of the semiconductor wafer, the back side of the semiconductor wafer being opposite to a front side of the semiconductor wafer; and
a plating layer disposed on the patterned metallization layer at least on a back side of the patterned metallization layer facing away from the semiconductor wafer, and
wherein the patterned metallization layer covers the back side of the semiconductor wafer except for the one or more kerf regions of the semiconductor wafer, and wherein the semiconductor wafer comprises one or more through-silicon (TS) diodes.

Assignees

• Infineon Technologies Ag

Inventors

• Fischer Thomas
• Ahrens Carsten
• Sojka Damian
• Schmenn Andre

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title