Electrical channel including pattern voids

US10153238B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10153238-B2
Application numberUS-201514696313-A
CountryUS
Kind codeB2
Filing dateApr 24, 2015
Priority dateAug 20, 2014
Publication dateDec 11, 2018
Grant dateDec 11, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A channel to be coupled to an input of a receiver, the channel including: a first transmission line including: a first trace; and a first reference plane including a plurality of first pattern voids overlapping the first trace.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic device comprising: a transmitter; a receiver coupled to the transmitter; a first transmission line coupled between the transmitter and the receiver, the first transmission line comprising: a first trace; a third trace; an insulating substrate; and a first reference plane on the insulating substrate, the first reference plane having a plurality of first pattern voids overlapping the first trace, the plurality of first pattern voids being filled with insulating substrate; and a second transmission line, wherein a first end of the second transmission line is coupled to the transmitter and a second end of the second transmission line is coupled to the receiver, wherein a first end of the first transmission line is coupled to the second end of the second transmission line at an input of the receiver to enhance reflections of a signal transmitted between the transmitter and the receiver, and wherein the first transmission line further comprises a resistor directly connecting the first trace to the third trace, such that a first end of the resistor is directly connected to the first trace and a second end of the resistor is directly connected to the third trace, at a second end of the first transmission line. 2. The electronic device of claim 1 , wherein each of the plurality of first pattern voids extends through the first reference plane. 3. The electronic device of claim 1 , wherein the second transmission line comprises: a second trace; and a second reference plane including a plurality of second pattern voids overlapping the second trace. 4. The electronic device of claim 3 , wherein the first transmission line is configured to enhance reflections of the signal at a first frequency, and the second transmission line is configured to suppress reflections of the signal at a second frequency different from the first frequency. 5. The electronic device of claim 1 , wherein the second transmission line comprises: a second trace; and a second reference plane having a continuous thickness along the second trace. 6. The electronic device of claim 1 , wherein the enhanced reflections of the signal transmitted between the first terminal and the second terminal, comprises a predefined frequency defined by a period between the plurality of first pattern voids. 7. A circuit board comprising: a first terminal to be coupled to a transmitter; a second terminal to be coupled to a receiver; a first transmission line coupled between the first terminal and the second terminal, the first transmission line comprising: a first trace; a third trace; an insulating substrate; and a first reference plane on the insulating substrate, the first reference plane having a plurality of first pattern voids overlapping the first trace, the plurality of first pattern voids being filled with insulating substrate; and a second transmission line, wherein a first end of the second transmission line is coupled to the first terminal and a second end of the second transmission line is coupled to the second terminal, wherein a first end of the first transmission line is coupled to the second end of the second transmission line at an input of the first terminal to enhance reflections of a signal transmitted between the first terminal and the second, and wherein a resistor connects the first trace to the third trace, such that a first end of the resistor is directly connected to the first trace and a second end of the resistor is directly connected to the third trace, at a second end of the first transmission line. 8. The circuit board of claim 7 , wherein each of the plurality of first pattern voids extend through the first reference plane. 9. The circuit board of claim 7 , wherein the second transmission line comprises: a second trace; and a second reference plane including a plurality of second pattern voids overlapping the second trace. 10. The circuit board of claim 9 , wherein the first transmission line is configured to enhance reflections of the signal at a first frequency, and the second transmission line is configured to suppress reflections of the signal at a second frequency different from the first frequency. 11. The circuit board of claim 7 , wherein the second transmission line comprises: a second trace; and a second reference plane having a continuous thickness along the second trace. 12. A channel to be coupled to an input of a receiver, the channel comprising: a first transmission line comprising: a first trace; a third trace; an insulating substrate; and a first reference plane on the insulating substrate, the first reference plane having a plurality of first pattern voids overlapping the first trace, the plurality of first pattern voids being filled with insulating substrate; and a second transmission line, wherein a first end of the second transmission line is to be coupled to a transmitter and a second end of the second transmission line is to be coupled to the receiver, wherein a first end of the first transmission line is coupled to the second end of the second transmission line at an input of the receiver to enhance reflections of a signal transmitted between the transmitter and the receiver, and wherein a second end of the first transmission line is terminated with a resistor connecting the first trace to the third trace, wherein a first end of the resistor is directly connected to the first trace and a second end of the resistor is directly connected to the third trace. 13. The channel of claim 12 , wherein each of the plurality of first pattern voids extends through the first reference plane. 14. The channel of claim 12 , wherein the second transmission line comprises: a second trace; and a second reference plane having a continuous thickness along the second trace. 15. The channel of claim 12 , wherein the second transmission line comprises: a second trace; and a second reference plane including a plurality of second pattern voids overlapping the second trace. 16. The channel of claim 15 , wherein: each of the plurality of second pattern voids extends through the first reference plane, and each of the plurality of second pattern voids extends through the second reference plane. 17. The channel of claim 12 , wherein the first transmission line is configured to enhance reflections of the signal at a first frequency, and the second transmission line is configured to suppress reflections of the signal at a second frequency different from the first frequency.

Assignees

Inventors

Classifications

  • Waveguides, e.g. strip lines · CPC title

  • H10W44/20Primary

    at high-frequency [HF] or radio frequency [RF] · CPC title

  • Microstrips; Strip lines · CPC title

  • Single or multiple openings in a shielding, ground or power plane (H05K1/0227 takes precedence) · CPC title

  • Skew reduction or using delay lines · CPC title

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Frequently asked questions

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What does patent US10153238B2 cover?
A channel to be coupled to an input of a receiver, the channel including: a first transmission line including: a first trace; and a first reference plane including a plurality of first pattern voids overlapping the first trace.
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W44/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 11 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).