Method for producing semiconductor device and semiconductor device

US10153227B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10153227-B2
Application numberUS-201715694994-A
CountryUS
Kind codeB2
Filing dateSep 4, 2017
Priority dateMar 29, 2017
Publication dateDec 11, 2018
Grant dateDec 11, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a through via extending through the semiconductor substrate from the first surface to the second surface, a metal layer adjacent an inside surface of the through via, and an insulating film including OH bonds located between the semiconductor substrate and the metal layer, the insulating film having a thickness of 1 μm or less.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a semiconductor substrate having a first surface and a second surface opposite the first surface; a through via extending through the semiconductor substrate from the first surface to the second surface; a metal layer adjacent an inside surface of the through via; and an insulating film including OH bonds located between the semiconductor substrate and the metal layer, the insulating film having a thickness of 1 μm or less. 2. The semiconductor device according to claim 1 , wherein the insulating film comprises silicon oxide. 3. The semiconductor device according to claim 1 , wherein the insulating film comprises a silicon oxide film and a silicon nitride film. 4. The semiconductor device according to claim 1 , wherein the insulating film includes moisture therein. 5. The semiconductor device according to claim 4 , wherein the insulating film has a thickness that is increased by 15% due to moisture therein. 6. The semiconductor device according to claim 1 , wherein the metal layer comprises a barrier metal layer and a seed metal layer including copper, the barrier metal layer covering a surface of the insulating film. 7. The semiconductor device according to claim 1 , wherein a bond ratio of an amount of Si—OH bonds to an amount of Si—O bonds in the insulating film is equal to or less than 15%. 8. A method of producing a semiconductor device, comprising: forming a hole through a semiconductor substrate; depositing an insulating film on a first surface of the semiconductor substrate and on an inside surface of the hole at a temperature of 150° C. or less, the insulating film having a thickness of at most 1 μm; forming a metal layer on the inside surface of the hole, the metal layer covering the insulating film; forming a through via on the metal layer; and annealing the insulating film for a predetermined time prior to forming the metal layer, wherein a bond ratio of an amount of Si—OH bonds to an amount of Si—O bonds in the insulating film is equal to or less than 15%. 9. The method according to claim 8 , wherein the insulating film comprises silicon oxide. 10. The method according to claim 8 , wherein the insulating film comprises a silicon oxide film and a silicon nitride film. 11. The method according to claim 8 , wherein the insulating film includes moisture therein. 12. The method according to claim 11 , wherein the insulating film has a thickness that is increased by 15% due to moisture therein. 13. The method according to claim 8 , wherein the metal layer comprises a barrier metal layer and a seed metal layer including copper, the barrier metal layer covering a surface of the insulating film. 14. A semiconductor device comprising: a semiconductor substrate having a first surface and a second surface opposite the first surface; a first through via on the first surface; a wiring structure on the first surface, the wiring structure being in contact with the first through via; a second through via extending through the semiconductor substrate from the first surface to the second surface thereof, the second through via contacting the wiring structure; a metal layer within the second through via; an insulating film having OH bonds located between the semiconductor substrate and the metal layer, the insulating film having a thickness of at most 1 μm; and a conductive bump on the second through via for connecting to an external semiconductor device. 15. The semiconductor device according to claim 14 , wherein the insulating film includes silicon oxide. 16. The semiconductor device according to claim 14 wherein the insulating film comprises a silicon oxide film and a silicon nitride film. 17. The semiconductor device according to claim 14 , wherein the insulating film includes moisture therein. 18. The semiconductor device according to claim 14 , wherein the metal layer comprises a barrier metal layer and a seed metal layer including copper, the barrier metal layer covering a surface of the insulating film. 19. The semiconductor device according to claim 14 , wherein a bond ratio of an amount of Si—OH bonds to an amount of Si—O bonds in the insulating film is equal to or less than 15%.

Assignees

Inventors

Classifications

  • characterised by the sidewall insulation · CPC title

  • comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

  • comprising etching via holes that stop on pads or on electrodes · CPC title

  • Dispositions of multiple bond pads · CPC title

  • Multiple bond pads having different sizes · CPC title

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Frequently asked questions

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What does patent US10153227B2 cover?
A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a through via extending through the semiconductor substrate from the first surface to the second surface, a metal layer adjacent an inside surface of the through via, and an insulating film including OH bonds located between the semiconductor substrate and the metal …
Who is the assignee on this patent?
Toshiba Memory Corp
What technology area does this patent fall under?
Primary CPC classification H10W20/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 11 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).