Patterning method and a method of fabricating a semiconductor device using the same

Patent metadata

Field	Value
Publication number	US-10153214-B2
Application number	US-201615386843-A
Country	US
Kind code	B2
Filing date	Dec 21, 2016
Priority date	Jan 15, 2016
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A patterning method for fabricating a semiconductor device includes forming, for example sequentially forming, a lower buffer layer, a first channel semiconductor layer, and a capping insulating layer on a substrate, forming an opening to penetrate the capping insulating layer and the first channel semiconductor layer and expose a portion of the lower buffer layer, forming a second channel semiconductor layer to fill the opening and include a first portion protruding above the capping insulating layer, performing a first CMP process to remove at least a portion of the first portion, removing the capping insulating layer, and performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding above the first channel semiconductor layer.

First claim

What is claimed is:

1. A patterning method for fabricating a semiconductor device, comprising:
forming a lower buffer layer, a first channel semiconductor layer, and a capping insulating layer on a substrate, the first channel semiconductor layer including a material having a lattice constant that is lower than a lattice constant of the lower buffer layer;
forming an opening to penetrate the capping insulating layer and the first channel semiconductor layer and to expose a portion of the lower buffer layer;
forming a second channel semiconductor layer to fill the opening, the second channel semiconductor layer including a first portion protruding upwardly with respect to a top surface of the capping insulating layer and including a material having a lattice constant that is higher than the lattice constant of the lower buffer layer;
performing a first CMP process to remove at least a portion of the first portion of the second channel semiconductor layer;
removing the capping insulating layer to expose a top surface of the first channel semiconductor layer; and
performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding upwardly with respect to the top surface of the first channel semiconductor layer,
wherein the first CMP process is performed using a first CMP slurry, and
the second CMP process is performed using a second CMP slurry, which is selected to allow the second semiconductor layer to be polished at a lower polishing rate than a polishing rate of the first CMP slurry.

2. The method of claim 1 , wherein
the first CMP process is performed to polish the first portion at a first polishing rate, and
the second CMP process is performed to polish the second portion at a second polishing rate lower than the first polishing rate.

3. The method of claim 1 , wherein the first CMP process is performed to allow a ratio in polishing rate of the first portion to the capping insulating layer to be in a range of from 40:1 to 100:1.

4. The method of claim 1 , wherein the first CMP slurry includes an acidic or basic solution containing a first polishing particle, a first oxidizing agent, a first pH regulator, and a polishing regulator, and
the second CMP slurry includes an acidic solution containing a second polishing particle, a second oxidizing agent, and a second pH regulator.

5. The method of claim 1 , wherein the lower buffer layer and the first channel semiconductor layer are formed by an epitaxial growth process using the substrate as a seed layer.

6. The method of claim 1 , wherein the second channel semiconductor layer is formed by a selective epitaxial growth process, in which the first channel semiconductor layer and the lower buffer layer in the opening are used as a seed layer.

7. The method of claim 1 , further comprising:
forming an upper buffer layer in the opening, before the forming of the second channel semiconductor layer.

8. A method of fabricating a semiconductor device, comprising:
preparing a substrate having a logic cell region, the logic cell region including an NMOSFET region and a PMOSFET region;
forming a first channel semiconductor pattern and a second channel semiconductor pattern on the NMOSFET region and the PMOSFET region, respectively; and
forming a gate electrode to cross both of the first and second channel semiconductor patterns,
wherein the forming of the first and second channel semiconductor patterns includes,
forming a lower buffer layer, a first channel semiconductor layer, and a capping insulating layer on the substrate,
removing at least a portion of the capping insulating layer and at least a portion of the first channel semiconductor layer to form an opening exposing the lower buffer layer on the PMOSFET region,
forming a second channel semiconductor layer to fill the opening and include a first portion protruding upwardly with respect to a top surface of the capping insulating layer,
performing a first CMP process to remove at least a portion of the first portion of the second channel semiconductor layer, removing the capping insulating layer to expose a top surface of the first channel semiconductor layer, and
performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding upwardly with respect to the top surface of the first channel semiconductor layer; and

patterning the first and second channel semiconductor layers to form trenches defining the first and second channel semiconductor patterns,
wherein the first CMP process is performed using a first CMP slurry, and
the second CMP process is performed using a second CMP slurry, which is selected to allow the second semiconductor layer to be polished at a lower polishing rate than a polishing rate of the first CMP slurry.

9. The method of claim 8 , wherein
the first CMP process is performed to polish the first portion at a first polishing rate, and
the second CMP process is performed to polish the second portion at a second polishing rate lower than the first polishing rate.

10. The method of claim 8 , wherein the first CMP process is performed to allow a ratio in polishing rate of the first portion to the capping insulating layer to be in a range of from 40:1 to 100:1.

11. The method of claim 8 , wherein
the first channel semiconductor layer includes a material having a same lattice structure as the lower buffer layer and having a lattice constant that is lower than a lattice constant of the lower buffer layer, and
the second channel semiconductor layer includes a material having a same lattice structure as the lower buffer layer and having a lattice constant that is higher than the lattice constant of the lower buffer layer.

12. The method of claim 8 , further comprising:
forming device isolation layers in the trenches, wherein the device isolation layers are formed to expose upper portions of the first and second channel semiconductor patterns.

13. The method of claim 8 , further comprising:
forming first source/drain regions at both sides of the gate electrode on the NMOSFET region; and
forming second source/drain regions at both sides of the gate electrode on the PMOSFET region,
wherein the first source/drain regions have a different conductivity type from the second source/drain regions.

14. The method of claim 8 , further comprising:
forming an upper buffer layer in the opening, before the forming of the second channel semiconductor layer.

15. The method of claim 14 , wherein the upper buffer layer includes the same material as the lower buffer layer.

16. The method of claim 8 , wherein
the logic cell region comprises a first logic cell region and second and third logic cell regions, which are spaced apart from each other in a first direction with the first logic cell region interposed therebetween,
the first channel semiconductor pattern is formed on the NMOSFET region of at least one of the first to third logic cell regions, and
the second channel semiconductor pattern is formed on the PMOSFET region of at least one of the first to third logic cell regions.

17. A method of fabricating a semiconductor device, the method comprising:
forming a first buffer layer, a first channel semiconductor layer and a capping layer on a substrate;
forming an opening in a portion of the first channel semiconductor layer and the capping layer to expose the first buffer layer;
forming a second buffer layer in the opening;
forming a second channel semiconductor layer on the second buffer layer to fil

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Se Jung
• Kim Ju-Hyun
• Kim Hoyoung
• Yoon Boun
• Kwon Taeyong
• Kim Sangkyun
• Park Sanghyun

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P52/402

  of semiconductor materials · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• F24B5/023

  Supply of primary air for combustion · CPC title

• F24H9/02

  Casings; Cover lids; Ornamental panels · CPC title