Integrated circuit for a stable electrical connection and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10153193-B2
Application number	US-201715615123-A
Country	US
Kind code	B2
Filing date	Jun 6, 2017
Priority date	Jun 15, 2016
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

An integrated circuit includes a substrate, a pad electrode disposed on the substrate, and a passivation layer disposed on the pad electrode and including an organic insulating material. The integrated circuit further includes a bump electrode disposed on the passivation layer and connected to the pad electrode through a contact hole. The passivation layer includes an insulating portion having a first thickness and covering an adjacent edge region of the pad electrode and the substrate, and a bump portion having a second thickness, that is greater than the first thickness, and covering a center portion of the pad electrode.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate;
a pad electrode disposed on the substrate;
a passivation layer disposed on the pad electrode and including an organic insulating material; and
a bump electrode disposed on the passivation layer in a first region of the substrate and connected to the pad electrode through a contact hole in a second region of the substrate,
wherein the passivation layer includes an insulating portion having a first thickness and covering an adjacent edge region of the pad electrode and the substrate, and a bump portion having a second thickness, that is greater than the first thickness, and covering a center portion of the pad electrode.

2. The integrated circuit of claim 1 , wherein
the bump portion of the passivation layer is disposed on the pad electrode.

3. The integrated circuit of claim 1 , wherein
the contact hole is disposed in an insulating portion of the passivation layer.

4. The integrated circuit of claim 1 , wherein
the pad electrode includes multiple layers.

5. The integrated circuit of claim 1 , further comprising
a protrusion disposed on an upper surface of the bump electrode.

6. The integrated circuit of claim 5 , wherein
the passivation layer further includes non-conductive particles.

7. The integrated circuit of claim 1 , wherein
the passivation layer includes a plurality of bump portions, and
the pad electrode overlaps at least two bump portions of the plurality of bump portions.

8. The integrated circuit of claim 1 , wherein the bump electrode is disposed on the bump portion of the passivation layer.

9. An integrated circuit comprising:
a substrate;
a pad electrode disposed on the substrate;
a passivation layer disposed on the pad electrode and including an organic insulating material; and
a bump electrode disposed on the passivation layer in a first region of the substrate and connected to the pad electrode through a contact hole in a second region of the substrate,
wherein the passivation layer includes an insulating portion having a first thickness and covering an adjacent edge region of the pad electrode and the substrate, and a bump portion having a second thickness, that is greater than the first thickness, and covering a center portion of the pad electrode, wherein
the bump portion of the passivation layer has a semicircular shaped cross-section.

10. The integrated circuit of claim 1 , wherein
the passivation layer includes a photosensitive organic material.

11. The integrated circuit of claim 10 , wherein
the passivation layer includes polyimide, polybenzoxazole, acryl, phenol, silicon, silicon modified polyimide, or epoxy-based polymer materials.

12. A method for manufacturing an integrated circuit, comprising:
forming a pad electrode on a substrate;
forming an organic insulating material layer on the pad electrode and the substrate;
patterning the organic insulating material layer to form a passivation layer including an insulating portion having a first thickness and covering an edge region of the pad electrode and at least part of the substrate, and a bump portion having a second thickness, that is greater than the first thickness, and covering a substantially center portion of the pad electrode; and
forming a bump electrode on the passivation layer in a first region of the substrate and connected to the pad electrode in a second region of the substrate.

13. The method of claim 12 , wherein
a slit mask or a half-tone mask is used in the patterning of the organic insulating material layer.

14. The method of claim 12 , further comprising
curing the passivation layer after forming the passivation layer.

15. The method of claim 12 , further comprising:
forming a metal seed layer on the passivation layer;
forming a photoresist pattern including an opening region on the metal seed layer;
growing the metal seed layer disposed inside the opening region using an electroplating method;
removing the photoresist pattern; and
etching the metal seed layer to remove a portion excluding a portion where the metal seed layer grows, and forming a bump electrode.

16. The method of claim 12 , further comprising
forming a contact hole in an insulating portion of the passivation layer and overlapping at least part of the pad electrode,
wherein the bump electrode is connected to the pad electrode through the contact hole.

17. The method of claim 12 , wherein
the bump portion of the passivation layer is disposed on the pad electrode.

18. The method of claim 12 , wherein
the bump portion of the passivation layer has a semicircular shaped cross-section.

19. The method of claim 12 , wherein
the organic insulating material layer includes polyimide, polybenzoxazole, acryl, phenol, silicon, silicon modified polyimide, or epoxy-based polymer materials.

20. The method of claim 12 , wherein
the organic insulating material layer includes non-conductive particles, and a protrusion is formed on an upper surface of the bump electrode.

21. The method of claim 12 , wherein
the passivation layer includes a plurality of bump portions, and
the pad electrode overlaps at least two of the plurality of bump portions.

Assignees

• Samsung Display Co Ltd

Inventors

• Yang Jeong Do
• Kim Byoung Yong
• Ryu Seung-Soo
• Song Sang Hyeon
• Jo Jung Yun
• Ha Seung-Hwa
• Hwang Jeong Ho

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title

• H10W72/255

  of outermost layers of multilayered bumps, e.g. material of a coating · CPC title