Semiconductor nanowire fabrication

Patent metadata

Field	Value
Publication number	US-10153158-B2
Application number	US-201415102553-A
Country	US
Kind code	B2
Filing date	Dec 8, 2014
Priority date	Dec 12, 2013
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

Methods are provided for fabricating semiconductor nanowires on a substrate. A nanowire template is formed on the substrate. The nanowire template defines an elongate tunnel which extends, laterally over the substrate, between an opening in the template and a seed surface. The seed surface is exposed to the tunnel and of an area up to about 2×10 4 nm 2 . The semiconductor nanowire is selectively grown, via said opening, in the template from the seed surface. The area of the seed surface is preferably such that growth of the nanowire proceeds from a single nucleation point on the seed surface. There is also provided a method for fabricating a plurality of semiconductor nanowires on a substrate and a semiconductor nanowire and substrate structure.

First claim

What is claimed is:

1. A method for fabricating a semiconductor nanowire on a substrate, the method comprising:
forming a nanowire template defining an elongate tunnel which extends, laterally over the substrate, between an opening in the template and a seed surface, the seed surface being exposed to the tunnel and of having an area up to about 2×10 4 nm 2 such that growth of the nanowire proceeds from a single nucleation point on the seed surface; and
via said opening, selectively epitaxially growing the semiconductor nanowire in the template from the seed surface, wherein selectively epitaxially growing the semiconductor nanowire is by one of: metal-organic vapor phase deposition; migration enhanced epitaxy; and hydride vapor phase epitaxy.

2. The method according to claim 1 , wherein the area of the seed surface is no greater than about 10 4 nm 2 .

3. The method according to claim 1 , wherein the seed surface has a width of up to about 100 nm and a breadth, perpendicular to said width, of up to about 100 nm.

4. The method according to claim 1 , wherein the seed surface occludes one end of the tunnel.

5. The method according to claim 4 , wherein the seed surface is perpendicular to the longitudinal axis of the tunnel.

6. The method according to claim 1 , wherein the seed surface is a monocrystalline semiconductor surface.

7. The method according to claim 1 , wherein the seed surface is a surface of consisting of at least one of: an amorphous semiconductor, a polycrystalline semiconductor, a metal, and a metal-semiconductor alloy.

8. The method according to claim 1 , wherein said elongate tunnel has one or more branches, defined by the template, extending therefrom.

9. The method according to claim 1 , wherein the substrate comprises a seed region, in the shape of the interior of said nanowire template, overlying and in contact with an insulating layer such that the insulating layer is exposed around the seed region, the method further comprising:
forming a masking layer in contact with the seed region and the insulating layer whereby the masking layer and insulating layer provide the nanowire template;
defining an opening in the masking layer to provide said opening in the nanowire template; and
via said opening, removing part of the seed region to form said tunnel whereby a remaining part of the seed region provides said seed surface.

10. The method according to claim 9 , the method further comprising:
patterning a seed layer overlying the insulating layer of the substrate to form said seed region and expose the insulating layer around the seed region.

11. The method according to claim 10 , wherein the substrate comprises a semiconductor-on-insulator wafer having a semiconductor layer providing said seed layer.

12. The method according to claim 1 , wherein the substrate comprises a seed layer, the method further comprising:
patterning the seed layer to form a seed region projecting from the surface of the seed layer; and
forming the nanowire template on the seed layer such that the seed region occludes one end of said tunnel and provides said seed surface.

13. The method according to claim 12 , wherein the seed region comprises at least one of: silicon, germanium and alloys thereof.

14. The method according to claim 1 , wherein the nanowire comprises a compound semiconductor material.

Assignees

• IBM

Inventors

• Borg Mattias Bengt
• Moselund Kirsten Emilie
• Riel Heike E
• Schmid Heinz

Classifications

• H10P14/276

  Lateral overgrowth · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1912

  using selective deposition, e.g. epitaxial lateral overgrowth [ELO] or selective deposition of single crystal silicon · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/2922

  being non-crystalline insulating materials, e.g. glass or polymers · CPC title