Timing controller, display device, and method of driving the same

Patent metadata

Field	Value
Publication number	US-10152908-B2
Application number	US-201514850626-A
Country	US
Kind code	B2
Filing date	Sep 10, 2015
Priority date	Nov 3, 2014
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A timing controller, a display device, and a method of driving the same able to prevent a dark defect that would otherwise be formed when two or more image control methods are disclosed.

First claim

What is claimed is:

1. A timing controller comprising:
a first compensation controller configured to generate first compensated image data by adding a first compensation value to image data according to a dithering pattern; and
a variable dithering controller configured to:
output the first compensated image data, responsive to the first compensated image data generated by adding the first compensation value to the image data according to the dithering pattern being equal to or smaller than a maximum grayscale level, and
generate modified first compensated image data by adding a modified first compensation value to the image data according to the dithering pattern such that the modified first compensated image data is equal to or smaller than the maximum grayscale level, responsive to the first compensated image data being greater than the maximum grayscale level,
wherein the variable dithering controller outputs the first compensated image data or the modified first compensated image data which is equal to or smaller than the maximum grayscale level.

2. The timing controller according to claim 1 , wherein the first compensation value comprises an image data compensation value in a predetermined first grayscale level area.

3. The timing controller according to claim 1 , wherein the image data comprises RGB data or WRGB data converted from the RGB data.

4. The timing controller according to claim 1 , further comprising a memory configured to save a plurality of sets of graph data describing a plurality of interpolation graphs that the variable dithering controller refers to when modifying the first compensated image data.

5. The timing controller according to claim 4 , wherein,
responsive to the first compensated image data being greater than the maximum grayscale level,
the variable dithering controller is configured (i) to select interpolation graph data among the plurality of sets of graph data, the selected interpolation graph data corresponding to an interpolation graph causing the first compensated image data to be equal to or smaller than the maximum grayscale level, (ii) to determine the modified first compensation value by referring to the selected interpolation graph data, the modified first compensation value being added to the image data to produce the modified first compensated image data equal to or smaller than the maximum grayscale level, and (iii) to output the modified first compensated image data equal to or smaller than the maximum grayscale level, the modified first compensated image data being produced by adding the modified first compensation value to the image data.

6. The timing controller according to claim 5 , wherein, responsive to the first compensated image data being greater than the maximum grayscale level, the variable dithering controller is configured to select interpolation graph data corresponding to an interpolation graph having a steeper gradient for a range of grayscale levels than a gradient of another interpolation graph used for generating the first compensated image data.

7. The timing controller according to claim 4 , wherein the plurality of interpolation graphs indicate first compensation values for a range of grayscale levels, and have different gradients in a subset of the range of grayscale levels.

8. The timing controller according to claim 1 , further comprising a second compensation controller configured to output the first compensated image data or second compensated image data by modifying the modified first compensated image data, based on a second compensation value.

9. The timing controller according to claim 8 , wherein the variable dithering controller is configured to output the second compensated image data responsive to the second compensated image data being equal to or smaller than the maximum grayscale level, and to output modified second compensated image data by modifying the second compensated image data such that the modified second compensated image data is smaller than or equal to the maximum grayscale level responsive to the second compensated image data being greater than the maximum grayscale level.

10. The timing controller according to claim 8 , wherein the second compensation value comprises an image data compensation value with which a difference in threshold voltages of transistors in subpixels is compensated.

11. A method of driving a display device comprising:
generating first compensated image data by adding a first compensation value to image data according to a dithering pattern;
outputting the first compensated image data generated by adding the first compensation value to the image data according to the dithering pattern responsive to the first compensated image data being smaller than or equal to a maximum grayscale level; and
generating and outputting modified first compensated image data by adding a modified first compensation value to the image data according to the dithering pattern such that the modified first compensated image data is equal to or smaller than the maximum grayscale level responsive to the first compensated image data being greater than the maximum grayscale level,
wherein the first compensated image data or the modified first compensated image data which is output is equal to or smaller than the maximum grayscale level.

12. A display device comprising:
a display panel comprising data lines, gate lines, and a matrix of subpixels disposed thereon;
a timing controller configured to generate output image data by modifying input image data based on a piece of variable dithering control data among a plurality of pieces of variable dithering control data variously defining compensation values for a range of grayscale levels, each of the plurality of pieces of variable dithering control data describing an interpolation graph of different compensation values for the range of grayscale levels; and
a data driver electrically connected to the timing controller and the data lines, the data driver configured to:
receive the output image data,
convert the output image data to data voltages, and
output the data voltages to the data lines,
wherein the output image data is equal to or smaller than a maximum grayscale level, and the output image data is generated by adding the compensation value to the input image data.

13. A display device comprising:
a display panel comprising data lines, gate lines, a matrix of subpixels disposed thereon;
a timing controller configured to:
generate compensated image data by modifying input image data according to a compensation value and a dithering pattern associated with the dithering pattern,
determining whether the compensated image data generated by modifying the input image data according to the compensation value and the dithering pattern is larger than a maximum grayscale level, and
generate output image data by adding a modified compensation value to the input image data according to determination of whether the compensated image data is larger than the maximum grayscale level; and

a data driver electrically connected to the timing controller and the data lines, the data driver configured to convert the output image data into data voltages and to output the data voltages to the data lines,
wherein subpixels to which the data voltages according to the image data corresponding to the maximum grayscale level are applied and a dark defect is not formed on the display panel.

14. The timing controller according to claim 7 , wherein the plurality of interpolation graphs have different gradients at a common compensation value.

15. The timing controller according to c

Assignees

• Lg Display Co Ltd

Inventors

• Pyeon Myungjin
• Chon Hyunson

Classifications

• G09G2320/0295

  by monitoring each display pixel · CPC title

• G09G3/2022 Primary

  using sub-frames · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title