Graphics processing systems
US-2016239939-A1 · Aug 18, 2016 · US
Hardware based free lists for multi-rate shader
US10152764B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10152764-B2 |
| Application number | US-201514666463-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 24, 2015 |
| Priority date | Mar 24, 2015 |
| Publication date | Dec 11, 2018 |
| Grant date | Dec 11, 2018 |
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Abstract
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A group of buffers are connected via pointers as free-lists implemented in hardware, such that shader information and output processing information can be efficiently accessed by a multi-rate shader. A free-list storage picks the first available entry. The first free entry that gets allocated then becomes a pointer to another entry.
First claim
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What is claimed is: 1. A method comprising: providing a storage with three buffers for multi-rate shading to avoid duplication between pixel rate and coarse pixel rate shading, including a first buffer for pixel rate shading, a second buffer for coarse pixel rate shading and a third buffer for pixel dispatch to reference said first and second buffers so that pixel rate or coarse pixel rate dispatch can use the first and second buffers or only the first buffer; and multi-rate shading in a hardware using said storage. 2. The method of claim 1 including storing bits in said first buffer to indicate whether a sample stored in said first buffer is unlit, failed a stencil test, or failed a depth test. 3. The method of claim 1 including storing centroids in said first buffer. 4. The method of claim 1 including storing different data in said first buffer depending on the type of multi-sample anti-aliasing. 5. The method of claim 1 including storing a pointer to said first buffer in said second buffer. 6. One or more non-transitory computer readable media storing instructions executed by a processor to perform a sequence comprising: providing a storage with three buffers for multi-rate shading to avoid duplication between pixel rate and coarse pixel rate shading, including a first buffer for pixel rate shading, a second buffer for coarse pixel rate shading and a third buffer for pixel dispatch to reference said first and second buffers so that pixel rate or coarse pixel rate dispatch can use the first and second buffers or only the first buffer; and multi-rate shading using said storage. 7. The media of claim 6 said sequence including storing bits in said first buffer to indicate whether a sample stored in said first buffer is unlit, failed a stencil test, or failed a depth test. 8. The media of claim 6 said sequence including storing centroids in said first buffer. 9. The media of claim 6 said sequence including storing different data in said first buffer depending on the type of multi-sample anti-aliasing. 10. The media of claim 6 said sequence including storing a pointer to said first buffer in said second buffer. 11. An apparatus comprising: a storage; and a hardware processor to provide a storage with three buffers for multi-rate shading to avoid duplication between pixel rate and coarse pixel rate shading, including a first buffer for pixel rate shading, a second buffer for coarse pixel rate shading and a third buffer for pixel dispatch to reference said first and second buffers so that pixel rate or coarse pixel rate dispatch can use the first and second buffers or only the first buffer, said storage to store states for multi-rate shading and multi-rate shader to use said storage. 12. The apparatus of claim 11 said processor to store bits in said first buffer to indicate whether a sample stored in said first buffer is unlit, failed a stencil test, or failed a depth test. 13. The apparatus of claim 11 said processor to store centroids in said first buffer. 14. The apparatus of claim 11 said processor to store different data in said first buffer depending on the type of multi-sample anti-aliasing. 15. The apparatus of claim 11 said processor to store a pointer to said first buffer in said second buffer.
Assignees
Inventors
Classifications
- G06T1/60Primary
Memory management · CPC title
Shading · CPC title
General purpose rendering architectures · CPC title
Filling planar surfaces by adding surface attributes, e.g. adding colours or textures · CPC title
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- What does patent US10152764B2 cover?
- A group of buffers are connected via pointers as free-lists implemented in hardware, such that shader information and output processing information can be efficiently accessed by a multi-rate shader. A free-list storage picks the first available entry. The first free entry that gets allocated then becomes a pointer to another entry.
- Who is the assignee on this patent?
- Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification G06T1/60. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 11 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).