Apparatus and method for physically unclonable function (PUF) for a memory array

Patent metadata

Field	Value
Publication number	US-10152613-B2
Application number	US-201815898935-A
Country	US
Kind code	B2
Filing date	Feb 19, 2018
Priority date	Jul 13, 2015
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes after applying a voltage to a memory array: determining a first duration between the applying of the voltage and a first output of a first bit cell, the first output corresponding to a first value stored in the first bit cell, and determining a second duration between the applying of the voltage and a second output of a second bit cell, the second output corresponding to a second value stored in the second bit cell. The example method further includes determining a function based on a comparison of the first duration and the second duration, the function to establish an identification of a circuit that includes the memory array.

First claim

What is claimed is:

1. An apparatus comprising:
a memory array;
a voltage source coupled to the memory array, the voltage source configured to apply a first voltage to the memory array;
a sense amplifier coupled to the memory array, the sense amplifier configured to output a second voltage, based on a comparison of a first read access time of a first bit cell of the memory array and a second read access time of a second bit cell of the memory array, after the voltage source applies the first voltage to the memory array; and
a processor coupled to the sense amplifier, the processor configured to determine a physically unclonable function based on the second voltage, the physically unclonable function identifying a circuit, the circuit including the memory array.

2. The apparatus of claim 1 , wherein:
the second voltage is a logical high voltage, in response to the sense amplifier determining that the first read access time is less than the second read access time; and
the second voltage is a logical low voltage, in response to the sense amplifier determining that the first read access time is greater than the second read access time.

3. The apparatus of claim 1 , wherein:
the second voltage is a logical low voltage, in response to the sense amplifier determining that the first read access time is less than the second read access time; and
the second voltage is a logical high voltage, in response to the sense amplifier determining that the first read access time is greater than the second read access time.

4. The apparatus of claim 1 , wherein the processor is further configured to:
receive, from a database over a network, an expected second voltage;
authenticate the circuit, in response to determining that the second voltage matches the expected second voltage; and
not authenticate the circuit, in response to determining that the second voltage does not match the expected second voltage.

5. The apparatus of claim 1 , wherein the processor is further configured to instruct the voltage source to apply the first voltage to the memory array, in response to the processor receiving a challenge message from a device, wherein the device is a database, an authentication host, or a physically unclonable function (PUF) generator.

6. The apparatus of claim 5 , wherein the challenge message indicates a bit pattern to write to bit cells of the memory array, the first voltage, bit cells of the memory array for reading, timing for reading bit cells of the memory array, response PUF data, or ranking for read access times of bit cells of the memory array.

7. The apparatus of claim 1 , wherein the processor is further configured to:
generate a key based on the physically unclonable function; and
transmit the key to a device, wherein the device is a database, a PUF generator, or an authentication host.

8. The apparatus of claim 1 , wherein the processor is further configured to:
transmit, to a device, a response, based on the second voltage, wherein the device is a database, a PUF generator, or an authentication host;
receive, from the device, a message;
utilize the memory array, in response to determining that the message is an approval signal; and
deactivate the memory array, in response to determining that the message is a disable signal.

9. The apparatus of claim 1 , wherein the processor is further configured to:
generate a keyed-hash message authentication code (HMAC), based on the second voltage; and
transmit, to an authentication host, the HMAC.

10. A method comprising:
applying, by a voltage source to a memory array, a first voltage;
outputting, by a sense amplifier, a second voltage, based on a comparison of a first read access time of a first bit cell of the memory array and a second read access time of a second bit cell of the memory array, after the voltage source applies the first voltage to the memory array; and
determining, by a processor, a physically unclonable function, based on the second voltage, the physically unclonable function identifying a circuit, the circuit including the memory array.

11. The method of claim 10 , wherein:
the second voltage is a logical high voltage, in response to the sense amplifier determining that the first read access time is less than the second read access time; and
the second voltage is a logical low voltage, in response to the sense amplifier determining that the first read access time is greater than the second read access time.

12. The method of claim 10 , wherein:
the second voltage is a logical low voltage, in response to the sense amplifier determining that the first read access time is less than second read access time; and
the second voltage is a logical high voltage, in response to the sense amplifier determining that the first read access time is greater than the second read access time.

13. The method of claim 10 , further comprising:
receiving, by the processor from a database over a network, an expected second voltage;
authenticating, by the processor, the circuit, in response to determining that the second voltage matches the expected second voltage; and
not authentication, by the processor, the circuit, in response to determining that the second voltage does not match the expected second voltage.

14. The method of claim 10 , wherein not authenticating the circuit comprises notifying a user of a lack of authentication.

15. The method of claim 10 , further comprising:
instructing, by the processor, the voltage source to apply the first voltage to the memory array, in response to receiving a challenge message from a device, wherein the device is a database, an authentication host, or a physically unclonable function (PUF) generator.

16. The method of claim 15 , wherein the challenge message indicates a bit pattern to write to bit cells of the memory array, the first voltage, bit cells of the memory array for reading, timing for reading bit cells of the memory array, response PUF data, or rankings for read access times of bit cells of the memory array.

17. The method of claim 10 , further comprising:
generating, by the processor, a key based on the physically unclonable function; and
transmitting, by the processor to a device, the key, wherein the device is a database, a PUF generator, or an authentication host.

18. The method of claim 10 , further comprising:
transmitting, by the processor to a device, a response, based on the second voltage;
receiving, by the processor from the device, a message, wherein the device is a database, a PUF generator, or an authentication host;
utilizing, by the processor, the memory array, in response to determining that the message is an approval signal; and
deactivating, by the processor, the memory array, in response to determining that the message is a disable signal.

19. The method of claim 10 , further comprising:
generating, by the processor, a keyed-hash message authentication code (HMAC), based on the second voltage; and
transmitting, by the processor to an authentication host, the HMAC.

20. A device comprising:
a circuit, comprising:
a static random access memory (SRAM) array; and
a sense amplifier; and

a memory controller configured to:
apply a first voltage to the SRAM array, wherein the sense amplifier is configured to output a second voltage based on a comparison of a first read access time of a first bit cell of the SRAM array and a second read access time of a second bit cell of the SRAM array, after a voltage source applies a voltage to the SRAM array; and

Assignees

• Texas Instruments Inc

Inventors

• Kwong Joyce
• Bittlestone Clive
• Goel Manish

Classifications

• G06F21/73 Primary

  by creating or determining hardware identification, e.g. serial numbers · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C29/50012

  of timing · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title