Deferred inter-processor interrupts

Patent metadata

Field	Value
Publication number	US-10152438-B2
Application number	US-201514867770-A
Country	US
Kind code	B2
Filing date	Sep 28, 2015
Priority date	Jan 15, 2013
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

First claim

What is claimed is:

1. A data processing system comprising:
a first processor;
a second processor;
an interrupt controller coupled to the first processor and to the second processor, the interrupt controller having a delayed inter-processor interrupt (IPI) register that is configured, when set by the first processor, to indicate that the first processor has requested a delayed IPI, the delayed IPI specifying a time value, and the interrupt controller having a timer to determine when a period defined by the time value expires, the period starting in response to the interrupt controller receiving the delayed IPI, and the interrupt controller being configured to wake up the second processor and to assign a runnable thread to the second processor to process the runnable thread when the timer expires, and wherein the interrupt controller is coupled to one or more devices or sources to receive interrupts for processing.

2. The system as in claim 1 wherein the interrupt controller comprises a cancel indicator that is configured to receive a cancel signal from the first processor to cancel the deferred IPI, and wherein when the timer's period expires and the cancel signal has not been received, the interrupt controller wakes up the second processor and assigns the runnable thread to the second processor for processing.

3. The system as in claim 2 wherein an interrupt handler in the first processor cannot be interrupted but a thread in either of the first processor or the second processor can be interrupted.

4. The system as in claim 3 wherein a scheduler, executing on the first processor, requests the deferred IPI.

5. The system as in claim 4 wherein the timer provides a representative time value to be used by the timer.

6. The system as in claim 4 wherein the first processor processes the runnable thread after cancelling the deferred IPI.

7. The system as in claim 6 wherein the data processing system has no priority scheme for interrupts.

8. The system as in claim 1 wherein the delayed IPI is cancelled in response to the first processor becoming available to process the runnable thread.

9. A method for data processing in a multiple processor system that includes a first processor and a second processor and an interrupt controller, the interrupt controller coupled to the first processor and the second processor and one or more devices or sources to receive interrupts for processing, the method comprising:
receiving at the first processor, from the interrupt controller, a second interrupt while the first processor is processing a first interrupt;
requesting, by the first processor in response to the second interrupt, a delayed inter-processor interrupt (IPI) by sending the delayed IPI to the interrupt controller, the delayed IPI specifying a time value;
starting a timer in the interrupt controller to determine when a period defined by the time value expires, the period starting in response to the interrupt controller receiving the delayed IPI; and
waking up the second processor and assigning a runnable thread to the second processor to process the runnable thread when the timer expires.

10. The method as in claim 9 wherein the interrupt controller comprises a cancel indicator that is configured to receive a cancel signal from the first processor to cancel the deferred IPI, and wherein when the timer's period expires and the cancel signal has not been received, the interrupt controller wakes up the second processor and assigns the runnable thread to the second processor for processing.

11. The method as in claim 10 wherein an interrupt handler in the first processor cannot be interrupted but a thread in either of the first processor or the second processor can be interrupted.

12. The method as in claim 11 wherein a scheduler, executing on the first processor, requests the deferred IPI.

13. The method as in claim 12 wherein the timer provides a representative time value to be used by the timer.

14. The method as in claim 12 wherein the first processor processes the runnable thread after cancelling the deferred IPI.

15. The method as in claim 14 wherein the data processing system has no priority scheme for interrupts.

16. The method as in claim 9 wherein the delayed IPI is cancelled in response to the first processor becoming available to process the runnable thread.

17. A machine readable non-transitory storage medium storing executable program instructions for data processing in a system that includes a first processor and a second processor and an interrupt controller, the interrupt controller coupled to the first processor and the second processor and one or more devices or sources to receive interrupts for processing, the executable program instructions, when executed by the system, causing the system to perform a method comprising:
receiving at the first processor, from the interrupt controller, a second interrupt while the first processor is processing a first interrupt;
requesting, by the first processor in response to the second interrupt, a delayed inter-processor interrupt (IPI) by sending the delayed IPI to the interrupt controller, the delayed IPI specifying a time value;
starting a timer in the interrupt controller to determine when a period defined by the time value expires, the period starting in response to the interrupt controller receiving the delayed IPI; and
waking up the second processor and assigning a runnable thread to the second processor to process the runnable thread when the timer expires.

18. The machine readable non-transitory storage medium as in claim 17 wherein the interrupt controller comprises a cancel indicator that is configured to receive a cancel signal from the first processor to cancel the deferred IPI, and wherein when the timer's period expires and the cancel signal has not been received, the interrupt controller wakes up the second processor and assigns the runnable thread to the second processor for processing.

19. The machine readable non-transitory storage medium as in claim 18 wherein an interrupt handler in the first processor cannot be interrupted but a thread in either of the first processor or the second processor can be interrupted.

20. The machine readable non-transitory storage medium as in claim 19 wherein a scheduler, executing on the first processor, requests the deferred IPI.

Assignees

• Apple Inc

Inventors

• Kumar Derek R
• De Cesare Joshua Phillips

Classifications

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• G06F9/4418

  Suspend and resume; Hibernate and awake · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• Y02D10/14

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title