Display panel and method for forming an array substrate of a display panel

Patent metadata

Field	Value
Publication number	US-10152159-B2
Application number	US-201715620680-A
Country	US
Kind code	B2
Filing date	Jun 12, 2017
Priority date	Apr 1, 2015
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

The present application provides a display panel. The display panel includes an array substrate which includes a display region and a frame region. The frame region includes a gate circuit drive unit, the gate circuit drive unit comprises a thin film transistor, and the thin film transistor comprises a source, a drain and a gate. The frame region further includes a driving circuit and a first signal lead line, the first signal lead line is arranged on a single layer and arranged on a same layer as the signal transmission wire layer, one end of the first signal lead line is electrically connected to the gate and the other end of the first signal lead line is electrically connected to the driving circuit.

First claim

What is claimed is:

1. A display panel comprising an array substrate, the array substrate comprising a display region and a frame region,
wherein the display region comprises a signal transmission wire layer,
wherein the frame region comprises a gate circuit drive unit, the gate circuit drive unit comprises a thin film transistor, and the thin film transistor comprises a source, a drain and a gate,
wherein the frame region further comprises a driving circuit and a first signal lead line, the first signal lead line is arranged on a same single layer as the signal transmission wire layer of the display region, wherein one end of the first signal lead line is electrically connected to the gate, and the other end of the first signal lead line is electrically connected to the driving circuit.

2. The display panel according to claim 1 , wherein the gate of the thin film transistor comprises: a stack of a first gate conductive layer and a second gate conductive layer, and a first gate insulating layer disposed between the first gate conductive layer and the second gate conductive layer;
wherein a first gate via is arranged between the first gate conductive layer and the second gate conductive layer, and wherein the second gate conductive layer is electrically connected to the first gate conductive layer through the first gate via.

3. The display panel according to claim 2 , wherein the second gate conductive layer is located on a same layer as the signal transmission wire layer.

4. The display panel according to claim 3 , wherein the display region further comprises an active layer, a gate layer, a source and drain layer, a pixel electrode layer and a common electrode layer, and the active layer, the gate layer, the source and drain layer, the pixel electrode layer, the common electrode layer and the signal transmission wire layer are arranged in a stacked manner.

5. The display panel according to claim 4 , wherein the first gate conductive layer is located on a same layer as the gate layer.

6. The display panel according to claim 3 , wherein the first signal lead line is electrically connected to the second gate conductive layer.

7. The display panel according to claim 3 , wherein the first signal lead line is electrically connected to the first gate conductive layer through a via.

8. The display panel according to claim 2 ,
wherein the source of the thin film transistor comprises a stack of a first source conductive layer and a second source conductive layer, and a first source insulating layer disposed between the first source conductive layer and the second source conductive layer, wherein a first source via is arranged between the first source conductive layer and the second source conductive layer, and the second source conductive layer is electrically connected to the first source conductive layer via the first source via,
wherein the drain of the thin film transistor comprises a stack of a first drain conductive layer and a second drain conductive layer, and a first drain insulating layer disposed between the first drain conductive layer and the second drain conductive layer, wherein a first drain via is arranged between the first drain conductive layer and the second drain conductive layer, and the second drain conductive layer is electrically connected to the first drain conductive layer via the first drain via, and
wherein the first source conductive layer and the first drain conductive layer are located on a same layer and are formed as a whole.

9. The display panel according to claim 1 , wherein the frame region further comprises a second signal lead line, the second signal lead line is arranged on a single layer and arranged on a same layer as the signal transmission wire layer of the display region, one end of the second signal lead line is electrically connected to the source, and the other end of the second signal lead line is electrically connected to the driving circuit.

10. The display panel according to claim 9 , wherein the source of the thin film transistor comprises: a first source conductive layer, a second source conductive layer, a third source conductive layer and a fourth source conductive layer, the first source conductive layer is electrically connected with the second source conductive layer through a first source via, the second source conductive layer is electrically connected to the fourth source conductive layer through a second source via, and the third source conductive layer is electrically connected to the fourth source conductive layer through a third source via.

11. The display panel according to claim 10 , wherein the fourth source conductive layer is located on a same layer as the signal transmission wire layer.

12. The display panel according to claim 11 , wherein the display region further comprises an active layer, a gate layer, a source and drain layer, a pixel electrode layer and a common electrode layer, and the active layer, the gate layer, the source and drain layer, the pixel electrode layer, the common electrode layer and the signal transmission wire layer are arranged in a stack.

13. The display panel according to claim 12 , wherein the second source conductive layer and the second drain conductive layer are located on a same layer as the source and drain layer of the display region.

14. The display panel according to claim 11 , the second signal lead line is electrically connected to the fourth source conductive layer.

15. The display panel according to claim 11 , the second signal lead line is electrically connected to one of the first source conductive layer, the second source conductive layer and the third source conductive layer through a via.

16. The display panel according to claim 11 , wherein the drain of the thin film transistor comprises a stack of a first drain conductive layer and a second drain conductive layer, and a first drain insulating layer disposed between the first drain conductive layer and the second drain conductive layer, wherein a first drain via is arranged between the first drain conductive layer and the second drain conductive layer, and the second drain conductive layer is electrically connected to the first drain conductive layer via the first drain via, and
wherein the first source conductive layer and the first drain conductive layer are located on a same layer and are formed as a whole.

17. The display panel according to claim 1 , wherein the frame region further comprises a third signal lead line, wherein the third signal lead line is arranged on a single layer and arranged on a same layer as the signal transmission wire layer of the display region, one end of the third signal lead line is electrically connected to the drain, and the other end of the third signal outgoing line is electrically connected to the driving circuit,
wherein the drain of the thin film transistor comprises a first drain conductive layer, a second drain conductive layer, a third drain conductive layer and a fourth drain conductive layer, the first drain conductive layer is electrically connected to the second drain conductive layer via a first drain via, the second drain conductive layer is electrically connected to the fourth drain conductive layer via a second drain via, and the third drain conductive layer is electrically connected to the fourth drain conductive layer via a third drain via.

18. The display panel according to claim 1 , wherein the display region further comprises a common electrode layer, and the common electrode layer and the signal transmission wire layer are arranged in a stack;
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Assignees

• Shanghai Tianma Micro Elect Co
• Tianma Micro Electronics Co Ltd
• Shanghai Tianma Micro Electronics
• Tianma Micro Electronics Co/ Ltd

Inventors

• Cao Zhaokeng
• Jin Huijun
• Li Xiaoye
• Wu Huangyao
• Zhu Di

Classifications

• G02F2201/123

  pixel · CPC title

• H01L33/36

  Electricity · mapped topic

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• H01L27/124

  Electricity · mapped topic

• H01L27/1259

  Electricity · mapped topic