Multi-core dynamic frequency control system

Patent metadata

Field	Value
Publication number	US-10152107-B2
Application number	US-201514923908-A
Country	US
Kind code	B2
Filing date	Oct 27, 2015
Priority date	Oct 9, 2015
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

First claim

The invention claimed is:

1. A method implemented by a multi-core processor, the method comprising:
determining whether a first core included in a multi-core processor is controlling a system frequency that drives the first core and one or more second cores also included in the multi-core processor; and
in response to determining that the first core is not controlling the system frequency, controlling a first core voltage of the first core using voltage control codes, independent from one or more second voltages of the one or more second cores, based upon one or more critical path measurements within the first core, wherein the voltage control codes are based upon the one or more critical path measurements and one or more offset values configured to prevent the first core from taking control of the system frequency.

2. The method of claim 1 wherein the determining further comprises:
detecting that thermometer code information generated from the one or more critical path measurements does not match frequency control information corresponding to the system frequency.

3. The method of claim 2 further comprising:
providing pervasive control codes from the multi-core processor to the programmable voltage regulator to control the first core voltage in conjunction with at least one of the one or more second voltages in response to the thermometer code matching the frequency control information.

4. The method of claim 1 further comprising:
providing the voltage control codes generated by voltage control logic internal to the first core to a programmable voltage regulator that controls the first core voltage.

5. The method of claim 4 wherein the controlling of the first core voltage further comprises:
decreasing the first core voltage until the one or more critical path measurements change; and
increasing the first core voltage based on the one or more offset values.

6. The method of claim 4 wherein the controlling of the first core voltage further comprises:
increasing the first core voltage based on the one or more offset values in response to determining that the first core voltage does not include a voltage margin.

7. The method of claim 1 wherein the first core and the one or more second cores are included in a first of a plurality of quadrants included in the multi-core processor, and wherein each of the plurality of quadrants utilize a different system frequency to control their corresponding plurality of cores.

Assignees

• IBM

Inventors

• Campisano Francesco A
• Drake Alan J
• Floyd Michael S
• Hui David T
• Owczarczyk Pawel
• Tiner Marshall D
• Yuan Xiaobin

Classifications

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• Y02D10/172

  Cross-Sectional Technologies · mapped topic