Synaptic transistor based on metal nano-sheet and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10147897-B2
Application number	US-201715703366-A
Country	US
Kind code	B2
Filing date	Sep 13, 2017
Priority date	Sep 13, 2016
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A synaptic transistor based on a metal nano-sheet and a method thereof are provided. A self-assembled floating gate layer is formed. The floating gate layer prevents leakage of electric charges transmitted from a channel layer, and also temporarily stores the transmitted electric charge. Thus, the synaptic transistor may be used as an effective memory for storing.

First claim

The invention claimed is:

1. A synaptic transistor based on a metal nano-sheet, comprising:
a gate electrode layer;
a buffer layer disposed on the gate electrode layer;
an insulating layer disposed on the buffer layer;
a self-assembled floating gate layer disposed on the insulating layer;
a channel layer disposed on the self-assembled floating gate layer;
a source electrode layer disposed on one side of the channel layer; and
a drain electrode layer disposed on the other side of the channel layer, the drain electrode layer being spaced apart from the source electrode layer,
wherein the self-assembled floating gate layer comprises a metal oxide layer disposed on an external surface thereof and formed by naturally oxidization, and a metal layer disposed inside thereof.

2. The synaptic transistor of claim 1 , wherein the self-assembled floating gate layer comprises at least one naturally oxidizing material selected from the group consisting of silver (Ag), copper (Cu), and aluminum (Al).

3. The synaptic transistor of claim 1 , wherein a metal layer disposed inside of the self-assembled floating gate layer comprises a floating electrode configured to store an electric charge transmitted from a channel layer.

4. The synaptic transistor of claim 1 , wherein a metal oxide layer disposed outer portion of the self-assembled floating gate layer is used as both of a tunneling layer and a blocking insulating layer.

5. A method of manufacturing a synaptic transistor based on a metal nano-sheet, comprising:
preparing a gate electrode layer;
forming a buffer layer on the gate electrode layer;
forming an insulating layer on the buffer layer;
forming a self-assembled floating gate layer on the insulating layer;
forming a channel layer on the self-assembled floating gate layer;
forming a source electrode layer on one side of the channel layer; and
forming a drain electrode layer on the other side of the channel layer, the drain electrode layer being spaced apart from the source electrode layer,
wherein the self-assembled floating gate layer comprises a metal oxide layer disposed on an external surface thereof and formed by naturally oxidization, and a metal layer disposed inside thereof.

6. The method of claim 5 , wherein in the forming the self-assembled floating gate layer, the self-assembled floating gate layer comprises at least one naturally oxidizing material selected from the group consisting of silver (Ag), copper (Cu), and aluminum (Al).

7. The method of claim 5 , wherein in the forming the self-assembled floating gate layer, the self-assembled floating gate layer is formed to have an aluminum (Al) layer at a thickness of 3 nm to 10 nm through a physical vapor deposition.

8. The method of claim 5 , wherein in the forming the drain electrode layer on the other side of the channel layer, which is spaced apart from the source electrode layer, the source electrode layer and the drain electrode layer are formed from a metal thin film.

Assignees

• Gwangju Inst Science & Tech

Inventors

• Yoon Myung Han
• Kim Chang Hyun

Classifications

• H01L29/7881

  Electricity · mapped topic

• H01L51/0516

  Electricity · mapped topic

• H01L51/0554 Primary

  Electricity · mapped topic

• H01L21/28273

  Electricity · mapped topic

• H01L51/0021

  Electricity · mapped topic