Dielectric sidewall structure for quality improvement in Ge and SiGe devices

Patent metadata

Field	Value
Publication number	US-10147829-B2
Application number	US-201615273880-A
Country	US
Kind code	B2
Filing date	Sep 23, 2016
Priority date	Sep 23, 2016
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. A dielectric layer is arranged over an upper surface of the silicon substrate, and extends over outer edges of the well region and includes an opening that leaves an inner portion of the well region exposed. An epitaxial pillar of SiGe or Ge extends upward from the inner portion of the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric sidewall structure surrounds the epitaxial pillar and has a bottom surface that rests on an upper surface of the dielectric layer.

First claim

What is claimed is:

1. A method, comprising:
receiving a substrate, the substrate including a well region;
forming a dielectric layer over an upper surface of the substrate and over an upper surface of the well region;
forming a silicon nitride layer over the dielectric layer;
forming a low-κ dielectric layer over the silicon nitride layer;
selectively removing a portion of the low-κ dielectric layer and an underlying portion of the silicon nitride layer to form a first recess that exposes an upper surface of the dielectric layer;
forming a conformal dielectric liner over an upper surface of the low-κ dielectric layer, along sidewalls of the low-κ dielectric layer, along sidewalls of the silicon nitride layer, and over the exposed upper surface of the dielectric layer to partially fill the first recess; and
carrying out a first etch with the conformal dielectric liner in place to remove portions of the conformal dielectric liner from the upper surface of the low-κ dielectric layer and from the upper surface of the dielectric layer, thereby leaving a portion of the conformal dielectric liner as a dielectric sidewall precursor structure along sidewalls of the low-κ dielectric layer and along sidewalls of the dielectric layer and while leaving an upper surface region of the dielectric layer exposed.

2. The method of claim 1 , wherein a thickness of the dielectric sidewall precursor structure as measured from an innermost sidewall of the dielectric sidewall precursor structure to the silicon nitride layer is greater than a thickness of the dielectric layer as measured from an upper surface of the dielectric layer to an upper surface of the substrate.

3. The method of claim 1 , further comprising:
carrying out a second etch, which is different from the first etch, to thin the dielectric sidewall precursor structure and concurrently remove the exposed upper surface region of the dielectric layer, thereby forming a second recess terminating at an upper surface of the well region.

4. The method of claim 3 , further comprising:
epitaxially growing a pillar of Ge or SiGe material in the second recess to entirely fill the second recess without voids or gaps.

5. The method of claim 4 , wherein the first etch is an anisotropic etch and the second etch is an isotropic etch.

6. The method of claim 4 , wherein the dielectric sidewall precursor structure and the dielectric layer have the same dielectric material composition as one another.

7. The method of claim 4 , wherein the dielectric sidewall precursor structure has a first etch rate and the dielectric layer has a second etch rate that differs from the first etch rate for the second etch.

8. The method of claim 7 , wherein the second etch rate is less than the first etch rate by thirty percent or less.

9. A method, comprising:
receiving a substrate;
forming a first dielectric layer over an upper surface of the substrate;
forming a second dielectric layer over the first dielectric layer;
selectively removing a portion of the second dielectric layer to form a first recess that exposes an upper surface of the first dielectric layer;
forming a conformal dielectric liner over an upper surface and along sidewalls of the second dielectric layer, and over the exposed upper surface of the first dielectric layer to partially fill the first recess;
carrying out a first etch to remove lateral portions of the conformal dielectric liner, thereby leaving a remaining portion of the conformal dielectric liner as a dielectric sidewall precursor structure along sidewalls of the second dielectric layer while leaving an upper surface region of the first dielectric layer exposed, wherein a thickness of the dielectric sidewall precursor structure as measured from an innermost sidewall of the dielectric sidewall precursor structure to a nearest sidewall of the second dielectric layer is greater than a thickness of the first dielectric layer as measured from an upper surface of the first dielectric layer to an upper surface of the substrate;
carrying out a second etch, which has a different etching character than the first etch, to thin the dielectric sidewall precursor structure and concurrently remove the exposed upper surface region of the first dielectric layer, thereby forming a second recess terminating at an upper surface of the substrate; and
forming a pillar of semiconductor material in the second recess.

10. A method of forming an integrated circuit (IC), comprising:
receiving a substrate including a well region having a first conductivity type;
forming a first dielectric layer over an upper surface of the substrate, the first dielectric layer extending over outer edges of the well region;
forming a second dielectric layer over an upper surface of the first dielectric layer;
forming an opening in the second dielectric layer;
forming a dielectric sidewall structure in the opening along inner sidewalls of the second dielectric layer, the dielectric sidewall structure having a bottom surface that rests on an upper surface of the first dielectric layer;
with the dielectric sidewall structure in place, removing a portion of the first dielectric layer to extend the opening and leave an inner portion of the well region exposed; and
forming an epitaxial pillar of SiGe or Ge extending upward from the inner portion of the well region, the epitaxial pillar including a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type.

11. The method of claim 10 , wherein the first dielectric layer and dielectric sidewall structure have the same dielectric material composition as one another.

12. The method of claim 10 , wherein the first dielectric layer has a first etch rate and the dielectric sidewall structure has a second etch rate that differs from the first etch rate for a predetermined etch, and wherein the first etch rate is between 70% and 130% of the second etch rate.

13. The method of claim 10 , wherein the upper and lower epitaxial regions of the epitaxial pillar correspond to a photodiode configured to absorb incident radiation at a predetermined wavelength or range of wavelengths, the method further comprising:
forming an aluminum copper layer over the substrate, wherein the aluminum copper layer includes an opening aligned over an upper surface of the epitaxial pillar and through which the incident radiation may pass through the aluminum copper layer to read the photodiode; and
forming an anti-reflective coating over the aluminum copper layer and lining the opening of the aluminum copper layer.

14. The method of claim 10 , wherein inner sidewalls of the dielectric sidewall structure have rounded upper surfaces, and where an upper surface of the epitaxial pillar flares outward over the rounded upper surfaces.

15. The method of claim 10 , wherein the first dielectric layer has innermost sidewalls that are aligned with innermost sidewalls of the dielectric sidewall structure.

16. The method of claim 10 , further comprising:
forming a silicon nitride layer over the dielectric layer, the silicon nitride layer having an inner sidewall that is spaced apart from an outer sidewall of the epitaxial pillar by the dielectric sidewall structure.

17. The method of claim 16 , further comprising:
forming a low-κ dielectric layer over the silicon nitride layer;
wherein an upper surface of the low-κ dielectric layer is co-planar with both an upper surface of the dielectric sidewall structure and an upper surface of the epitaxial pilla

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chih-Ming
• Tseng Lee-Chuan
• Liu Ming Chyi
• Liu Po-Chun

Classifications

• H01L31/02161

  Electricity · mapped topic

• H01L31/1037

  Electricity · mapped topic

• H01L31/02019

  Electricity · mapped topic

• H01L31/103

  Electricity · mapped topic

• H01L31/105

  Electricity · mapped topic