Enhanced method of stressing a transistor channel zone

Patent metadata

Field	Value
Publication number	US-10147818-B2
Application number	US-201514950416-A
Country	US
Kind code	B2
Filing date	Nov 24, 2015
Priority date	Nov 25, 2014
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A method of straining a transistor channel zone is provided, including a) forming a plurality of stress blocks based on a material having an intrinsic stress, around a zone based on a semiconducting material in which a transistor channel will be made and on which a transistor gate will be formed, the stress blocks inducing a stress in the zone; b) forming a gate block on the zone, the gate block being disposed between the stress blocks; and c) at least partially removing the stress blocks without removing the gate block, wherein the gate block has a Young's modulus and a thickness such that the stress blocks are at least partially removed in step c) and the induced stress is at least partially maintained in the zone after the stress blocks are at least partially removed.

First claim

The invention claimed is:

1. A method for making a device comprising at least one strained semiconducting zone configured to be a transistor channel, the method comprising, in the following order:
a) forming a plurality of stress blocks based on a material having an intrinsic stress, around a zone based on a semiconducting material in which the transistor channel will be made and on which a transistor gate will be formed, the stress blocks inducing a stress in the zone;
b) forming a gate block on the zone, the gate block being disposed between the stress blocks; and
c) removing the stress blocks without removing the gate block,
wherein the gate block has a Young's modulus and a thickness such that the stress blocks are removed in step c) and the induced stress is at least partially maintained in the zone after the stress blocks are removed.

2. The method according to claim 1 , wherein the gate block is formed by depositing at least one gate dielectric and at least one gate material.

3. The method according to claim 1 , wherein the gate block comprises at least one dielectric material deposited on the semiconducting material, the gate dielectric material having a Young's modulus higher than that of the semiconducting material in the zone.

4. The method according to claim 3 , wherein the gate dielectric material is a High-k type material.

5. The method according to claim 4 , wherein the gate dielectric material is HfO 2 or Al 2 O 3 or HfSiO x N y .

6. The method according to claim 1 , further comprising:
forming a sacrificial gate on said zone before step a), the stress blocks formed in step a) being disposed in contact with the sacrificial gate; and
removing the sacrificial gate after step a) and before step b).

7. The method according to claim 6 , further comprising thermal annealing before removing the sacrificial gate, to cause expansion of the sacrificial gate.

8. The method according to claim 1 , further comprising, after step c):
depositing a layer based on a stress material having an intrinsic elastic stress; and
performing thermal annealing.

9. The method according to claim 1 , further comprising forming insulating spacers in contact with lateral flanks of the gate block, after step c).

10. The method according to claim 1 , wherein the material having the intrinsic stress is a dielectric material, the method further comprising forming insulating spacers in the dielectric material.

11. The method according to claim 1 ,
wherein the zone forms part of a region of a surface layer delimited by at least one trench filled with an insulating material, and
wherein the zone is supported on a layer of the insulating material,
the method further comprising performing thermal annealing to cause creep in the insulating material, after step b).

12. The method according to claim 1 , wherein the zone is located in a surface layer of a semiconductor on insulator type substrate and is supported on an insulating layer of the semiconductor on insulator type substrate, the insulating layer being supported on a semiconducting layer.

13. The method according to claim 1 , wherein the device comprises a FinFET type transistor, the zone being located in a semiconducting bar of the FinFET type transistor.

14. The method according to claim 1 , wherein the device comprises a strained channel transistor comprising at least one strained semiconducting zone configured to be a transistor channel.

15. The method according to claim 1 , wherein the stress blocks are formed directly on the semiconducting material in which the transistor channel will be made.

Assignees

• Commissariat Energie Atomique
• Commissariat Energie Atomique

Inventors

• Reboh Shay
• Mathieu Benoit

Classifications

• H01L29/7849 Primary

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/517

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic