Array substrate, manufacturing method thereof, and display device

US10147643B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10147643-B2
Application numberUS-201615521079-A
CountryUS
Kind codeB2
Filing dateSep 7, 2016
Priority dateJan 11, 2016
Publication dateDec 4, 2018
Grant dateDec 4, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate, a signal line disposed on the base substrate, an extinction layer disposed between the base substrate and the signal line, the extinction layer being configured to reduce an ambient light when the array substrate is located on a light exiting side. An orthographic projection of the signal line in a plane of the base substrate is coincided with an orthographic projection of the extinction layer in the plane of the base substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. An array substrate, comprising: a base substrate; a signal line disposed on the base substrate; and an extinction layer disposed between the base substrate and the signal line, the extinction layer including two opposite surfaces, a plurality of protrusion structures are disposed on the two opposite surfaces of the extinction layer, and the extension layer being configured to reduce an ambient light entering the signal line when the array substrate is located on a light exiting side, wherein an orthographic projection of the signal line in a plane of the base substrate is coincided with an orthographic projection of the extinction layer in the plane of the base substrate. 2. The array substrate according to claim 1 , wherein a material of the extinction layer comprises amorphous silicon or semiconductor mixture doped with amorphous silicon. 3. The array substrate according to claim 1 , wherein the extinction layer has a thickness satisfying an interference extinction formula: d =(2 n+ 1)λ/4 N   (1) where d is a thickness of the extinction layer, λ is a wavelength of the visible light in the air, N is a refractive index of the extinction layer, n is a natural number. 4. The array substrate according to claim 3 , wherein the thickness of the extinction layer is 340 Å. 5. The array substrate according to claim 1 , wherein the signal line is a gate line, or a common electrode line. 6. A display device, comprising the array substrate according to claim 1 , wherein the array substrate is located on a light exiting surface of the display device. 7. The array substrate according to claim 2 , wherein the extinction layer has a thickness satisfying an interference extinction formula: d =(2 n+ 1)λ/4 N   (1) where d is a thickness of the extinction layer, λ is a wavelength of the visible light in the air, N is a refractive index of the extinction layer, n is a natural number. 8. The array substrate according to claim 7 , wherein the thickness of the extinction layer is 340 Å. 9. A method for manufacturing an array substrate, comprising: providing a base substrate; and forming a patterned extinction layer and a patterned signal line on the base substrate by a single patterning process, the patterned extinction layer including two opposite surfaces; wherein the forming of the patterned extinction layer includes forming a plurality of protrusion structures on the two opposite surfaces of the extinction layer. 10. The method for manufacturing the array substrate according to claim 9 , further comprising: sequentially depositing an extinction layer and a metal layer on a surface of the base substrate; etching the metal layer by a mask, and forming a patterned signal line; and etching the extinction layer by using a pattern of the signal line, and forming a patterned extinction layer which has the same pattern as the patterned signal line. 11. The method for manufacturing the array substrate according to claim 10 , further comprising: placing the base substrate in a vacuum chamber, and performing a roughening treatment to a surface of the base substrate by a plasma gas, to allow a plurality of protrusion structures to be formed on a surface of a subsequently formed extinction layer near the base substrate. 12. The method for manufacturing the array substrate according to claim 10 , further comprising: depositing an extinction layer on a surface of the base substrate; placing the base substrate deposited with the extinction layer in a vacuum chamber, and performing a roughening treatment to the extinction layer by a plasma gas, to allow a plurality of protrusion structures to be formed on the extinction layer; and depositing a metal layer on the roughening treated extinction layer. 13. The method for manufacturing the array substrate according to claim 11 , further comprising: depositing an extinction layer on a surface of the base substrate; placing the base substrate deposited with the extinction layer in a vacuum chamber, and performing a roughening treatment to the extinction layer by a plasma gas, to allow a plurality of protrusion structures to be formed on the extinction layer; and depositing a metal layer on the roughening treated extinction layer.

Assignees

Inventors

Classifications

  • using masks for conductive or resistive materials · CPC title

  • H10D84/01Primary

    Manufacture or treatment · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • H01L21/77Primary

    Electricity · mapped topic

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What does patent US10147643B2 cover?
An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate, a signal line disposed on the base substrate, an extinction layer disposed between the base substrate and the signal line, the extinction layer being configured to reduce an ambient light when the array substrate is located on a light exiting side. An orthograph…
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Beijing Boe Display Tech Co, Beijing Boe Display Techology Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D84/01. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 04 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).