Video processing unit and method of buffering a source video stream

Patent metadata

Field	Value
Publication number	US-10147463-B2
Application number	US-201514708947-A
Country	US
Kind code	B2
Filing date	May 11, 2015
Priority date	Dec 10, 2014
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

In a video system, a video source, e.g., a camera, provides a source video stream. The source video stream comprises a stream of image data units. A buffer control unit writes the image data units consecutively to a circular buffer. A display control unit reads the image data units consecutively from the circular buffer to generate a target video stream in accordance with a read delay. The display control unit comprises a feedback loop which controls timing of the operation of reading the image data units from the circular buffer so as to reduce a difference between the read delay and a reference delay. The video system may, for example, be installed in a vehicle, e.g., for providing a driver with a live view from a camera.

First claim

The invention claimed is:

1. A video processing unit, connected or connectable to a video source so as to receive a source video stream from the video source, the source video stream comprising a stream of image data units forming a stream of video frames; wherein the video processing unit comprises:
a buffer controller to write the image data units consecutively to a circular buffer, wherein the size of the circular buffer is less than a frame size of the source video stream; and
a display controller arranged to read the image data units consecutively from the circular buffer to generate a target video stream with a vertical synchronization, the display controller having a read delay associated with it, said read delay being a delay of said operation of reading the image data units from the circular buffer relative to said operation of writing the image data units to the circular buffer;
wherein the display controller forms part of a feedback loop arranged to control timing of said operation of reading the image data units from the circular buffer so as to reduce a difference between the read delay and a reference delay, wherein the feedback loop includes a delay detector and a comparator, the comparator configured to compare said read delay received from the delay detector with the reference delay and provide a delay correcting variable to the display controller to prevent the display controller from reading invalid image data units from the circular buffer, the delay detector configured to measure the read delay on the basis of the source video stream and the target video stream, the delay detector having a first input coupled to the video source for receiving the source video stream, and the delay detector coupled to receive a pixel clock signal and a vertical synchronization signal from the display controller, wherein the vertical synchronization signal indicates the vertical synchronization of the target video stream, wherein the delay detector includes a counter arranged to start counting in response to a vertical synchronization symbol in the source video stream and to stop counting in response to a vertical synchronization symbol in the target video stream.

2. The video processing unit of claim 1 , wherein the reference delay is between 20% and 80% of the duration of a fill cycle of the circular buffer.

3. The video processing unit of claim 1 , wherein said operation of controlling timing of said operation of reading the image data units from the circular buffer comprises adjusting one or both of a vertical synchronization gap and a horizontal synchronization gap of the target video stream.

4. The video processing unit of claim 1 , wherein the read delay is the time between a vertical synchronization symbol in the source video stream and the next vertical synchronization symbol in the target video stream.

5. The video processing unit of claim 1 , wherein the counter is synchronized with the display controller and arranged to measure the read delay.

6. The video processing unit of claim 1 , wherein the delay detector comprises a second input connected to the display controller for receiving the target video stream.

7. The video processing unit of claim 1 , wherein the video source is connected or connectable to a first clock so as to be clocked by the first clock and wherein the display controller is connected or connectable to a second clock so as to be clocked by the second clock, wherein the first clock and the second clock are operable independently.

8. The video processing unit of claim 1 , connected or connectable to a video display which is arranged to be driven by the target video stream.

9. The video processing unit of claim 1 , wherein the video source is a camera.

10. A vehicle comprising the video processing unit of claim 9 , wherein the camera is mounted in or on the vehicle.

11. The vehicle of claim 10 , wherein the camera is mounted near a rear section of the vehicle and oriented to provide a backward view.

Assignees

• Staudenmaier Michael Andreas
• Aubineau Vincent
• Martinez Pelayo Ioseph E
• Nxp Usa Inc

Inventors

• Staudenmaier Michael Andreas
• Aubineau Vincent
• Martinez-Pelayo Ioseph E

Classifications

• G11B31/006 Primary

  with video camera or receiver · CPC title

• H04N5/77 Primary

  between a recording apparatus and a television camera · CPC title

• G11B27/326

  used signal is a video-frame or a video-field (P.I.P.) · CPC title