Self-organized critical CMOS circuits and methods for computation and information processing

Patent metadata

Field	Value
Publication number	US-10147045-B2
Application number	US-201615346538-A
Country	US
Kind code	B2
Filing date	Nov 8, 2016
Priority date	May 11, 2014
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A circuit that makes use of chaos or self-organized criticality to generate a matrix of bits for computation and information processing. The example embodiment utilizes CMOS circuitry and can solve optimization problems. A plurality of unit cells includes multiple transistors in a lattice formation that set voltages as state variables to other transistor cells. Adjustable bifurcation parameters are utilized to bring the chaotic circuit in and out of the chaotic regime. A processing unit with software are utilized for implanting a problem of interest into the chaotic circuit, while data latches or analog to digital converters provide for reading out the voltages from the chaotic circuit.

First claim

What is claimed is:

1. An apparatus for solving optimization problems, comprising:
(a) a circuit lattice having a plurality of unit cells interconnected by a matrix of transmission gates;
(b) wherein each unit cell is configured for setting a voltage as a state variable on a node in the circuit lattice for each unit cell position; and
(c) wherein a transmissive mode of each transmission gate from said matrix of transmission gates is configured for being set in response to receiving a control signal to establish the transmissive mode of said transmission gate;
(d) a controller configured for outputting bifurcation control signals to change operating characteristics of at least a portion of the unit cells, and for outputting coupling strength control signals for changing transmission characteristics of said transmission gates when implanting an objective function in said circuit lattice; and
(e) a voltage registration circuit configured for registering state variable voltages in said circuit lattice and outputting these state variable voltages as digital signals to said controller;
(f) wherein said controller is configured for implanting a problem of interest into the circuit lattice, and for controlling bifurcation to drive said circuit lattice between chaos, self-organized critical, or Markovian regimes by modifying bifurcation parameters, until a desired solution is obtained.

2. The apparatus as recited in claim 1 , wherein the unit cells can be arranged in many different shapes of lattice formation.

3. The apparatus as recited in claim 1 , wherein the unit cells can have any number of connections to their neighboring cells.

4. The apparatus as recited in claim 1 , wherein said change in operating characteristics of the unit cells changes between having a stable state output, to that of having an oscillating output signal, depending on the state of the bifurcation control signal received.

5. The apparatus as recited in claim 1 :
wherein each said unit cell comprises a number of active elements within an oscillator circuit having a forward path through which an oscillator signal propagates and a feedback path from oscillator circuit output to oscillator circuit input; and
wherein said oscillator circuit is configured for having one of its stages selectively enabling or disabled through which the oscillator signal propagates in response to receiving said bifurcation signal.

6. The apparatus as recited in claim 1 , wherein the unit cells comprise a plurality of inverters connected in series.

7. The apparatus as recited in claim 6 , wherein one or more of the inverters, from said plurality of inverters, can be bypassed or turned off changing a mode of the unit cell from an oscillator mode to that of a circuit having steady states.

8. The apparatus as recited in claim 1 , wherein said transmission gate is configured so that the transmissive mode of resistance in said transmission gate changes in response to receiving said coupling strength control signals.

9. The apparatus as recited in claim 8 , wherein said transmission gate is further configured with polarity reversal so that opposing voltages are forced at opposing ends of said transmissive gate.

10. The apparatus as recited in claim 1 , wherein said controller comprises a digital control circuit configured for outputting control signals to the unit cells and transmission gates and for processing voltage states read from the circuit lattice.

11. The apparatus as recited in claim 10 , wherein said controller comprises at least one processing element and at least one memory configured for storing instructions executable on the processing element.

12. The apparatus as recited in claim 1 , wherein said voltage registration circuit comprises latch circuits configured for converting voltage signals at nodes of said lattice circuit to digital signals readable by said controller.

13. The apparatus as recited in claim 12 , wherein each said latch circuit upon receiving a clock signal digitizes and records a voltage signal at one node of said circuit lattice.

14. The apparatus as recited in claim 1 , wherein said voltage registration circuit comprises analog to digital conversion for converting voltage signals at nodes of said circuit lattice to digital signals which can be read by said controller.

15. The apparatus as recited in claim 1 , wherein the state variable voltages output as digital signals to said controller output from the voltage registration circuit, as a matrix of bits, represent a solution to the problem of interest, which is interpreted by the controller, which records the lowest objective function value (cost of a solution) and the solution that gives the lowest objective function value.

16. The apparatus as recited in claim 1 , further comprising:
a plurality of noise sources;
wherein said circuit or system operates in a self-organized phase; and
wherein width of the self-organized phase is controlled by modifying amplitude of the noise sources.

17. The apparatus as recited in claim 1 , wherein the chaotic circuit comprises a plurality of non-linearly coupled oscillators connected through said circuit lattice formation.

18. The apparatus as recited in claim 1 , wherein said desired solution is obtained based on an objective function value, called a cost function, of these solutions to the objective function.

19. The apparatus as recited in claim 18 , wherein said cost function of the solutions is determined from the circuit lattice, or determined by utilizing a computer processor configured for analyzing cost functions.

Assignees

• Univ California

Inventors

• Wang Kang L
• Chang Hao-Yuan

Classifications

• G06N7/01

  Probabilistic graphical models, e.g. probabilistic networks · CPC title

• G06N7/08 Primary

  using chaos models or non-linear system models · CPC title

• G06N7/005

  Physics · mapped topic