Expanded distribution unit

Patent metadata

Field	Value
Publication number	US-10146735-B2
Application number	US-201615019234-A
Country	US
Kind code	B2
Filing date	Feb 9, 2016
Priority date	Feb 10, 2015
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

The invention relates to a method for processing real-time data in a distribution unit of a distributed computer system, the computer system comprising a plurality of node computers and distribution units, the distribution unit containing, in addition to a switching engine (SE) and a switching memory (SM), one or more application computers each with one or more application central processing units and each with one or more application memories (AM), wherein the switching engine of the distribution unit, when it receives, at one of its ports, a message intended for an application computer, forwards this message to the addressed application computer through a direct memory access (DMA) unit that is arranged between the switching memory and the application memory of the addressed application computer and that is under the control of the switching engine. The invention also relates to an expanded distribution unit and a computer system with such expanded distribution units.

First claim

We claim:

1. A method for processing real-time data in a distribution unit of a distributed computer system, the distributed computer system comprising node computers and the distribution unit, the distribution unit comprising a switching engine ( 130 ), a switching memory ( 140 ), and one or more application computers ( 220 , 230 ) comprising one or more application central processing units ( 223 , 233 ) and one or more application memories ( 222 , 232 ), wherein the switching engine ( 130 ) of the distribution unit:
receives, at one of its ports ( 121 , 122 , 123 ), a message intended for an application computer of the one or more application computers; and
forwards the message to an addressed application computer ( 220 , 230 ) of the one or more application computers through a direct memory access (DMA) unit ( 221 , 231 );
wherein the DMA unit is arranged between the switching memory ( 140 ) and an application memory of the one or more application memories ( 222 , 232 ) of the addressed application computer ( 220 , 230 ) and is controlled by the switching engine ( 130 ),
wherein the distributed computer system comprises a time-triggered computer system, in which the switching engine ( 130 ) and the one or more application computers have access to a global sparse time base, and the switching engine outputs, at global time points contained in a schedule created a priori, a command to the DMA unit arranged between the switching memory and the one or more application computers, the command instructing to start a DMA transfer of data from the switching memory to the one or more application memories and to start a DMA transfer of data from the one or more application memories to the switching memory.

2. The method of claim 1 , wherein the source and destination addresses of the data that the DMA is to transport between the switching memory and the application memory, or vice versa, are contained in a schedule of the switching engine.

3. The method of claim 1 , wherein during transport intervals, no CPU ( 223 , 233 ) of the application computer ( 220 , 230 ) accesses an area of its memory that is affected by the transport.

4. The method of claim 1 , wherein both time-triggered and event-driven messages are transported and processed in the distribution unit.

5. The method of claim 1 , wherein the data is transported according to the TTEthernet protocol.

6. A distribution unit for processing real-time data in a distributed computer system, the distributed computer system comprising node computers and distribution units, the distribution unit comprising:
a switching engine ( 130 );
a switching memory ( 140 );
one or more application computers ( 220 , 230 ), each of the one or more application computers having one or more application central processing units ( 223 , 233 ) and one or more application memories ( 222 , 232 ); and
direct memory access (DMA) units ( 221 , 231 ) arranged between the switching memory ( 140 ) of the distribution unit and the one or more application memories ( 222 , 232 ) of the one or more application computers ( 220 , 230 ), the DMA units having control lines running from the switching engine ( 130 ) of the distribution unit to each of the DMA units, the control lines enabling the transport of commands from the switching engine ( 130 ) to the DMA units ( 221 , 231 ) for DMA transfer of memory areas of the switching memory ( 140 ) to memory areas of the one or more application memories and for transfer of the memory areas of the one or more application memories to memory areas of the switching memory ( 140 ),
wherein the distributed computer system comprises a time-triggered computer system, in which the switching engine ( 130 ) and the one or more application computers have access to a global sparse time base, and the switching engine outputs, at global time points contained in a schedule created a priori, a command to the DMA unit arranged between the switching memory and the one or more application computers, the command instructing to start a DMA transfer of data from the switching memory to the one or more application memories and to start a DMA transfer of data from the one or more application memories to the switching memory.

7. The distribution unit of claim 6 , wherein the control lines ( 301 ) are provided between the switching engine ( 130 ) and two or more, or all, of the one or more application computers ( 220 ).

8. The distribution unit of claim 6 , wherein at least one application computer of the one or more application computers is realized as a multiprocessor system.

9. The distribution unit of claim 8 , wherein all of the one or more application computers are realized as multiprocessor systems.

10. The distribution unit of claim 6 , wherein all subsystems of the distribution unit are implemented on a single highly integrated VLSI chip.

11. A computer system comprising multiple node computers and distribution units, wherein the computer system comprises one or more distribution units of claim 6 .

Assignees

• Fts Computertechnik Gmbh

Inventors

• Poledna Stefan
• Kopetz Hermann
• Schwarz Martin

Classifications

• H04L67/10

  in which an application is distributed across nodes in the network (software deployment G06F8/60; multiprogramming arrangements G06F9/46) · CPC title

• H04L49/35 Primary

  Switches specially adapted for specific applications · CPC title

• G06F13/282 Primary

  Cycle stealing DMA (G06F13/30 takes precedence) · CPC title

• G06F15/17331 Primary

  Distributed shared memory [DSM], e.g. remote direct memory access [RDMA] · CPC title

• G06F12/0835

  for main memory peripheral accesses (e.g. I/O or DMA) · CPC title